Lab

EE 421L: Digital Integrated Circuit Design Lab - Lab 7

Author: Gonzalo Arteaga

Email: arteag1@unlv.nevada.edu

Due Date: 11/8/2017

Link to directory: << lab7>>

Lab 7: Using Buses and Arrays in the design of word inverters, muxes, and high-speed adders

In this lab we design the basic building blocks of an ALU.

4-bit Inverter

Wide wires (buses) can be used to make large schematics more concise.

One example of this would be in the drafting of a 4-bit inverter. Instead of drawing out 4 individual inverters, one can instantiate a single inverter and create and array of 4 inverters in the edit object properties window.

In the image below there is an array of 4 inverters: I1<0>, I1<1>, I1<2>, and I1<3>.

(This inverter uses NMOS and PMOS sizes of W/L = 6u/0.6u)

Figure 1: 4-bit inverter schematic

Figure 2: 4-bit inverter symbol

The performance of the four bit adder was simulated with the following schematic.

The same input pulse was fed into all four inverters with varying capacitive loads. Note that the thin wires attached to the wide wire have to be labelled with their corresponding outputs.

In the simulation below, the outputs are organized from top to bottom in order of increasing capacitance for the load.

From the simulation, we see that as the capacitive load increases, the output’s delay time, rise time, and fall time increases. This is due to the increase in the time constant Tau = R*C.

Figure 3: Schematic for simulating 4-bit inverters

Figure 4: 4-bit adder simulation results

8-bit input/output gates:

8-bit NAND gate

For the 8-bit NAND gate, the NAND gate from lab 6 was used.

Its symbol was instantiated and wide wires were used to connect the pins to the inputs/outputs.

Figure 5: 8-bit NAND gate schematic

Figure 6: 8-bit NAND gate symbol

8-bit NOR gate

First, a single two-input NOR gate was assembled using 6u/0.6u NMOS and PMOS devices and a symbol was created. This symbol was then instantiated as an array of 8 NOR gates. Buses were used to connect pins to the symbol.

Figure 7: NOR gate schematic

Figure 8: NOR gate symbol

Figure 9: 8-bit NOR gate schematic

Figure 10: 8-bit NOR gate symbol

8-bit AND gate

The individual AND gate was made using the NAND gate designed in lab 6 with an inverter on its output. A symbol was created for the AND gate and it was instantiated into an array of 8 AND gates.

All devices used were sized 6u/0.6u

Figure 11: AND gate schematic

Figure 12: AND gate symbol

Figure 13: 8-bit AND gate schematic

Figure 14: 8-bit AND gate symbol

8-bit OR gate

Using the NOR gate from above (Figure7) and an inverter, the individual OR gate was made. A symbol was created and it was then used to make the 8-bit OR gate.

Figure 15: OR gate schematic

Figure 16: OR gate symbol

Figure 17: 8-bit OR gate schematic

Figure 18: 8-bit OR gate symbol

Simulation

The 8-bit gates were simulated using the following schematic. From the results of the simulation we see that the gates perform as expected.

Figure 19: 8-bit gate simulation schematic

Figure 20: 8-bit gates simulation results

2:1 MUX/DEMUX

The multiplexer/de-multiplexer was designed according to the following schematic. It is comprised of two transmission gates with control inputs such that only one transmission gate is on at a given time. The control input Si is the complement of the control input S. When S is at logic 1, the bottom transmission gate turns off while the top transmission gate turns on and connects input A to the output.

When used for de-multiplexing, the control inputs select whether input Z is fed to A or B.

Figure 21: 2:1MUX/DEMUX schematic

Figure 22: 2:1MUX/DEMUX symbol

Simulation

The MUX/DEMUX was simulated with following schematic. The left side of the schematic was set up for multiplexing and the right side for de-multiplexing.

As shown in the transient response, the MUX outputs signal B when the control input S is “low” and outputs A when S is “high”.

For the DEMUX, input Y is fed to output D when the control input S is “low” and to C when S is “high”.

From 0 to 20 nanoseconds, output C is floating at around zero volts and after 20 ns output D floats above VDD=5volts.

Figure 23: schematic for simulating 2:1MUX/DEMUX

Figure 24: simulation results for 2:1MUX/DEMUX

After this, the MUX/DEMUX was redesigned with an inverter so that there would only be one control input. This was then used to create an 8-bit array of 2 to 1 MUX/DEMUX.

Figure 25: re-designed 2:1MUX/DEMUX schematic

Figure 26: re-designed 2:1MUX/DEMUX symbol

Figure 27: 8-bit wide word 2:1MUX/DEMUX schematic

Figure 28: 8-bit wide word 2:1MUX/DEMUX symbol

Simulating the 8-bit wide 2:1MUX/DEMUX

The following schematic was used to simulate the 8-bit wide 2:1MUX/DEMUX. The transient response shows that the MUX/DEMUX performs as expected.

Figure 29: 8-bit MUX/DEMUX schematic for simulation

Figure 30: Simulation results for 8-bit MUX/DEMUX

AOI Implementation of a Full Adder

A Full adder was implemented using AND-OR-INVERT logic functions. Compared to the logic gate implementation of the full adder designed in lab 6, this Full Adder has significantly lower delay. The schematic of the Full Adder is shown below.

Figure 31: AOI Full Adder schematic

Figure 32: AOI Full Adder symbol

8-bit Full Adder

Figure 33: 8-bit Full Adder schematic

Figure 34: 8-bit Full Adder symbol

Simulation of 8-bit Adder

The following schematic was used for simulating the 8-bit adder.

In the schematic, input A corresponds to the number 13 {00001101} and input B corresponds to 200 {11001000}. With no Cin, the output should be 213 or {11010101}.

The simulation shows the desired results.

Figure 35: 8-bit Full Adder simulation schematic

Figure 36: 8-bit Full Adder simulation results

Layout of AOI Full-Adder

The standard frame for the layout of the AOI Full Adder (shown below) was made so that 5 horizontal wires could be laid out between the NMOS and the PMOS. Horizontal wiring was reserved for metal_2 and vertical wiring was reserved for metal_1. An empty space was left for Cout to be wired to the Cin of the next Full Adder.