EE 421L:  Digital Integrated Circuit Design Lab - Lab 1

Author:  Gonzalo Arteaga

Email:  arteag1@unlv.nevada.edu

Due Date:  September 6, 2017 

  

Lab Description

In this lab we go through part of Cadence Tutorial 1: Layout and Simulation of a Resistive Voltage Divider.

 

Pre-Lab

The Pre-Lab consists of obtaining a CMOSedu account so that the lab report webpages can be created on the CMOSedu website.

Also, I reviewed the steps to editing webpages.

 

Lab

First, Cadence must be setup for use with ON’s C5 process. After Cadence was completely setup we go to the Xterm window.

To start Cadence, change the directory to CMOSedu and then type virtuoso & into the terminal window.

 

 

Once Cadence starts up, the Command Interpreter Window and the Library Manager windows should appear. Create a library called

Tutorial_1 with the AMI 0.60u C5N process library attached.

 

As a side note, when we need to simulate examples done in class we first unzip the file, move it into the CMOSedu directory and then

Add the statement: DEFINE Filename $HOME/CMOSedu/Filename

The statement: DEFINE Filename /home/arteag1/CMOSedu/Filename is equivalent.

 

 

In the Tutorial_1 library, create a cell view schematic named R_div.

Assemble the following voltage divider schematic,

 

 

Once the schematic has been assembled, in the top left, select the check and save button before simulating the schematic.

Then, in the Command Interpreter Window make sure that there are no errors in the schematic.

 

 

Next, open up the Analog Design Environment using the Launch tab in the top left. Then select a Transient analysis for 1 second

And also select the outputs from the schematic.

 

The resulting ADE window should look like this,

 

 

To avoid having to set this all up again, go to the session tab in the ADE window and select Save State.

Then select the Save State Option as Cell View and press ok. Next time, this exact cell view can be loaded  with Load State.

 

Once the analysis and the outputs are set up, press the green Netlist and Run button.

The following window should open,

 

 

The above schematic shows that the input voltage at 1v and the output voltage as 0.5v which is to be expected since the input voltage is divided between two resistor of equal resistance.

 

2) In regards to saving the work completed in this lab and in future labs, the labs will be downloaded from the CMOSedu directory,

 

 

Then the file will be zipped up and placed in a Google Drive drop box or a Thumb Drive.

 

 

 

 

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