EE 421L: Digital Integrated Circuit Design Lab - Lab
3
Due Date: 9/20/2017
This lab consists of
the laying out of the Digital-to-analog converter from the previous lab using
n-well resistors.
Laying out a resistor
Before laying out an
n-well resistor one should know the sheet resistance of the n-well. For this
process, the sheet resistance of the n-well is approximately 819 ohms/square.
Next, the length and width of the resistor is chosen using the following
formula,
When choosing the
dimensions of the resistor, it’s important to know that the lengths and widths
have to be multiples of lambda, which is 300 nm for
this process.
For the 10kohm
resistor, the width was chosen as 4.5 um (15 lambda) and the length 56.1 um
(187 lambda). Using the equation from above the resistance is,
The resistor layout
is pictured below as well as its respective schematic and extracted view.
Figure 1: Resistor layout view
|
Figure 2: Resistor extracted view |
Figure 3: Resistor schematic |
**Note: To measure
the length and width of the resistor in Virtuoso Layout Suite, press K to create a ruler. Select a corner of
the resistor where the n-tap cell ends and the n-well begins then drag the
cursor to the other end of the n-well. To remove the rulers, press Shift+K.
DAC Layout
Using the resistor from above, the
basic R-2R structure of the DAC was laid out. This layout consisted of three
10kohm resistors stacked on top of one another in a single column. The spacing
between the resistors was chosen as the minimum spacing between n-wells or 5.4
um (18 lambda). The layout is shown below with the
respective pins labelled.
|
Figure 4: Layout of R-2R structure |
Figure 5: R-2R schematic |
This basic structure
was then repeatedly instantiated into the Mydesign_10-bit_DAC
cell from the previous lab. Wiring between the various cells was done on the
Metal1 layer. A portion of the DAC is shown below.
Figure 6: DAC layout
Once the layout of
the DAC was completed, a final DRC check was made to ensure no errors remain.
Then, the layout view was extracted and an LVS was performed on the schematic
view and the extracted view.
Figure 7: Output of LVS
Simulation:
When simulating the
extracted layout of the DAC, the tolerance setting in the ADE had to be
re-adjusted to avoid convergence issues.
In the ADE window,
under Simulation >> Options >> Analog the following settings
were used,
Figure 8:
Tolerance Settings
With no load on the DAC, the following results were achieved,
|
Figure 9: Simulating the DAC |
Figure 10：Plot of layout simulation |
Looking at the simulation above we see that the layout of the DAC
performs as expected.
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