EE 421L: Digital Integrated Circuit Design Lab - Lab
2
Due Date: 9/13/2017
1) Provide narrative to
the steps.
Download the lab2 zip file to the desktop, unzip the
file, then upload it to the CMOSedu
directory. Open the cds.lib file with the default text editor and add the line DEFINE lab2 $HOME/CMOSedu/lab2.
Start Cadence and look for the lab2 library which was
just added and then select the cell view sim_Ideal_ADC_DAC and open it.
Open the Analog Design Environment window, load the spectre_state, and run the simulation. The following should
appear,
(Colors have been changed to
demonstrate an understanding of how to change the graph’s characteristics)
The simulation shows an input voltage “Vin” being fed
into a 10-bit ideal ADC. The output of this ADC, B[9:0]
is a 10 bit binary number that represents the input signal. When B[9:0] is all zeroes, this corresponds to the input signal
being at 0 volts and when every digit in B[9:0] is 1, then it corresponds to an
input voltage of 5 volts. The least significant bit corresponds to a voltage
change of 4.88 mV.
Finally, Vout is B[9:0] converted back into an analog signal that resembles
Vin but is stair-cased.
2) Provide and discuss
simulation results different from the above to illustrate you understanding
The image above shows
an input signal that has been discretized into 5 steps. Each step corresponds
to an increase of 4.88 mV.
To determine the least significant bit, the entire
voltage range is divided by 1024 (this is the case for our example because 
)
Since VDD = 5 volts, the LSB corresponds to a voltage
of,
The above image shows a small signal that has been
discretized into two states to show the LSB.
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Design of 10-bit DAC:
The design of the
10-bit DAC is based on Fig. 30.14 in the CMOS textbook.
First, a cell view
was created for the basic resistor structure of the DAC and a symbol was
generated as well. The resistances where all 10kOhms and the 2R resistors where
modelled as 2 individual R resistors.
This symbol was then
cascaded one on top of another to form the 10-bit DAC.
Creating Symbol view:
To create a symbol for
the DAC, the ideal DAC cell, from the lab2 zip file, was copied over to another
cell view and the ideal DAC symbol was edited so that it would match our
design.
Determining output
resistance:
To determine the
output resistance of the DAC, all the inputs to the DAC are grounded and then
the resistors are combined in series and in parallel like shown below. Once
this is performed, the output resistance is found to be R=10kohms.
Delay when driving
capacitive load:
When determining the
delay of the DAC with a capacitive load, inputs B8 through B0 where grounded
and a voltage pulse was connected to input B9. To calculate the delay, the
resistors in the DAC are combined in series and in parallel as was done above.
The resulting
schematic is shown below,
Because of the
voltage divider, the steady state voltage across the capacitor will be half of
VDD. The delay is measured at the point when the capacitor voltage (Vc) reaches half of its final
voltage. This corresponds to 0.7*Time Constants after the voltage pulse.
Using this equation,
the delay time is estimated as 70 nanoseconds. Pictured below is the simulation
results which shows Td = 69.9 ns.
Simulations:
|
No Load:
|
With
no load on the DAC, the output voltage matches with the Ideal_DAC
sim shown above. |
|
Capacitive Load
(10pF):
|
With
a 10 pF capacitive load, the output voltage’s magnitude is decreased to 4.125
volts and it lags behind the input voltage by approximately 70.2 nanoseconds. |
|
Resistive Load:
|
Having
a 10 kohm resistive load on the DAC causes the
output to be divided by two since the output resistance forms a voltage
divider. |
|
Resistor and
Capacitor Load:
|
With
a 10 kohm resistor and a 10 pF capacitor as a load,
the output voltage’s magnitude is cut roughly in half and it also lags behind
the input by approximately 50 nanoseconds. |
Discussion:
In a real circuit the switches seen above
(the outputs of the ADC) are implemented with transistors (MOSFETs).
What happens when the
resistance of the switches isn’t small compared to R?
If the resistance of
the switches isn’t small compared to R, then a greater amount of the input
voltage will dissipate through that resistance resulting in a decrease in the
output voltage.
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