Lab

Lab 6 - EE 421L

Authored by Surafel Abera

Abera@unlv.nevada.edu

October 25, 2017

Pre-lab work:

Lab work Back-up	Tutorial 4 completed

Lab Work:

Draft a schematic and layout for a full adder using NAND and XOR gates

2-Input NAND and XOR gate Schematics

6u/0.6u NAND	6u/0.6 XOR

The realization of NAND and XOR gates were first started by drafting the schematics seen above. The symbols of
each circuit is created inorder to impleament the gates for the rest of the lab and for future lab projects.

NAND Symbol	XOR Symbol

The symbols above have the shape of the corresponding gate function. The NAND and XOR symbols each contain circuit that will function as their logical symbol represents. Next the functionality of the gates is checked by simulating the inputs and outputs of the gates using the truth table as a reference.

Schematic and Simulation of 12u/6u inverter, NAND, and XOR

Schematic of inverter, NAND, and XOR

Simulated using Specter

Truth Table

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/Sim_NAND_XOR_INV_schem.JPG

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/Sim_NAND_XOR_INV.JPG

A	B	NAND
0	0	1
0	1	1
1	0	1
1	1	0

A	B	XOR
0	0	0
0	1	1
1	0	1
1	1	0

The inputs for each gate is a voltage pulse source that can represent the logic "0" as voltage value of "0 V" or ground and the logic "1" is represented as "5 V". The simulation shows the gates i constructed mach the truth table outputs for the given inputs. Once the gates are tested for valid logic the layout process begins.

Layout of the NAND, and XOR

NAND Layout	XOR Layout

During the layout process the gates were constructed so that the the gates can be placed in parallel and having the same height. This method allows for the power and ground to be roughted above and below. Each gate has passed the DRC and the LVS net-list maches.

NAND DRC and LVS	XOR DRC and LVS

Schematic and Layout of the Full Adder

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/Full%20Adder/Full%20Adder_Schematic.JPG

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/Full%20Adder/Full%20Adder_Layout.JPG

The Full Adder schematic is relized by using the NAND and XOR gates created above. The Full Adder circuit is then laid out using the layout of each gate and they were placed next to eachother in parallel and power is roughted at the top of the layout and ground on the bottom of the layout.

Full Adder Symbol	Full Adder Layout DRC and LVS

The Full Adder circuit is contained in the Full Adder symbol which can be used for simulating the Full Adder or it can be used as part of a more complicated circuit.

Simulation of Full Adder

Simulated using Specter

Truth Table

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/sim_full_adder.JPG

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab6/sim_full_adder%20plot.JPG

A	B	Cin	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

The full adder circuit is simulated by using three pulsed voltage source. Inputs "A", "B", "Cin" are attaced to V0, V1, and V2 respectively will produce outputs "S" and "Cout".

Lab6 files

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