Lab 5 - EE 421L 

Authored by Surafel Abera

Abera@unlv.nevada.edu

October 11, 2017

 

Pre-lab work: 

Lab work Back-upTutorial 3 completed
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/backup.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/tutorial3.JPG
    
   
   
Lab work:
 

                                                    Inverter Schematics

 12u/6u inverter48u/24u inverter
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/12u_6u%20schematic.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20schematic.JPG
The schematic on the left is an inverter of (12u/6u) composed of four terminal NMOS W=6u L=0.6u , PMOS W=12u, L=0.6u.
The schematic on the right is four inverters in parallel [4* (12u/6u) = (48u/6u)].   Each inverter NMOS W=6u L=0.6u , PMOS W=12u, L=0.6u.
The 48u/24u inverter performs 4 times better than the 12u/6u inverter.       

     
 12u/6u Symbol48u/24u Symbol
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/12u_6u%20symbol.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20symbol.JPG

       

 12u/6u Layout48u/24u Layout
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/12u_6u%20layout.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20layout.JPG

In the layout the inverter terminals are handled differently than the schematics.  The body of the Pmos is connected to global vdd! through ntap.

The body of the Nmos is connected to ground (gnd!).

The layout of 48u/12u has 4 gates, sources, and drains that are connected together.

 

 12u/6u DRC and LVS48u/24u DRC and LVS
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/12u_6u%20DRC.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/12u_6u%20LVS.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20DRC.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20LVS.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/48u_24u%20LVS.JPG

    
Specter and UltraSim Simulation of 12u/6u inverter               


12u/6u inverter driving 100fF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_100f%2012u_6u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_100f%2012u_6u%20inverter_plot.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra12/ultra_100f_12u_6u_plot.JPG
     12u/6u inverter driving 1pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_1p%2012u_6u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_1p%2012u_6u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra12/ultra_1p_12u_6u_plot.JPG
     12u/6u inverter driving 10pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_10p%2012u_6u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_10p%2012u_6u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra12/ultra_10p_12u_6u_plot.JPG
     12u/6u inverter driving 100pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_100p%2012u_6u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/12u_6u/cap_100p%2012u_6u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra12/ultra_100p_12u_6u_plot.JPG
The 12u/6u inverter drives the smaller capacitor loads one time, but as the load capacitance is increased  it took longer time to charge the larger capacitor.
The plots of the Specter and UltraSim plots are equal.
   

  

  

       

Specter and UltraSim Simulation of 48u/24u inverter

48u/24u inverter driving 100fF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_100f%2048u_24u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_100f%2048u_24u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra48/ultra_100f_48u_24u_plot.JPG
48u/24u inverter driving 1pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_1p%2048u_24u%20inverter_schematic.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_1p%2048u_24u%20inverter_plot.JPG
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra48/ultra_1p_48u_24u_plot.JPG
48u/24u inverter driving 10pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_10p%2048u_24u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_10p%2048u_24u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra48/ultra_10p_48u_24u_plot.JPG
48u/24u inverter driving 100pF capacitorSimulated using SpecterSimulated using UltraSim
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_100p%2048u_24u%20inverter_schematic.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/48u_24u/cap_100p%2048u_24u%20inverter_plot.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/lab5/ultra48/ultra_100p_48u_24u_plot.JPG
The 48u/24u inverter performs better than the 12u/6u inverter in driving the different size of capacitors because it has he larger channel to conduct current.  
The plots of the Specter and UltraSim plots are equal.
     


  

   

Lab5 files

   

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