Lab 2 - EE 421L 

Authored by Surafel Abera

Abera@unlv.nevada.edu

September 13, 2017


Pre-lab work:

 I back-up my work on Onedrive

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/backup.JPG

I unzip this directory and added "DEFINE lab2 $HOME/CMOSedu/lab2" to my cds.lib in the design directory.  
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/cds_lib_define.JPG

Schematic view of the cell sim_Ideal_ADC_DAC

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/lab2_library_manager.JPG

Ideal 10-bit ADC and DAC

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/sim_ideal_adc_dac_schematic%20_9_04_17.JPG

 

Runing the simulation of Ideal 10-bit ADC and DAC

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/plot_sim_ideal_adc_dac%20_9_04_17.JPG

 

Runing the simulation of Ideal 10-bit ADC and DAC

 

Frequency is set to 10MHz                                                                Offset is set to 2.5mV

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/10Meg%20ideal%20adc-dac.JPG   http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/2.5mV%20offset%20ideal%20adc-dac.JPG

 

The value of the least significant bit is calculated using the formula in this lab the ideal ADC_DAC schematic the VDD is set to 2.5V with 2.5V offset there for 2.5V is the max amplitude of the signal.

 


Lab Report Documentation:

        Once i created a 10 bit DAC using 10K ohm then i created a symbol for it from Cellview.

    http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/10K_10-bit%20DAC%20Symbol.JPG  http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/10K_10-bit%20DAC%20Symbol.JPG 

How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and series

 http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Resistance%20parallel%20series.jpg

 
The value of the least significant bit is calculated using the formula VDD/2^N.  In this lab the ideal ADC_DAC schematic the VDD is set to 2.5V with 2.5V offset there for 2.5V is the max amplitude of the signal.

   http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/formula.JPG

 
Delay, Driving a Load
        Using the delay time formula Td= 0.7RC = 0.7(10K)(10p)=70ns

 http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Delay%20driving%2010pF%20Schematic.JPG          http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Delay%20driving%2010pF.JPG  

   

        First i copied the schematic cell view sim_Ideal_ADC_DAC to a cell sim2_Ideal_ADC_DAC and replaced the ideal DAC with the one i just designedhttp://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Sim2_Ideal_ADC_DAC%20schematic.JPG    http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Sim2_Ideal_ADC_DAC%20Plot.JPG 
 
        The 10K ohm load adds to the circuits resistance and acts as a voltage divider there for the output voltage is cut by half.
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010K%20Sim2_Ideal_ADC_DAC%20schematic.JPG  http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010K%20Sim2_Ideal_ADC_DAC%20plot.JPG
 
        Adding the capacitor smooths out the output voltage, adds a delay, and decrease the output voltage.

http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010pF%20Sim2_Ideal_ADC_DAC%20schematic.JPG  http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010pF%20Sim2_Ideal_ADC_DAC%20plot.JPG
        Adding RC in parallel affects the amplitude and adds a delay to the output.
http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010Kohm%20and%2010pF%20Sim2_Ideal_ADC_DAC%20schm.JPG  http://cmosedu.com/jbaker/courses/ee421L/f17/students/abera/Lab2/Driving%2010Kohm%20and%2010pF%20Sim2_Ideal_ADC_DAC%20plot.JPG
 
Explain what happens if the DAC drives a 10k load?
 
    A 10K load would cut the output voltage in half becouse the circuit and the load act as a voltage divider.

       Discuss what happens if the resistance of the switches isn't small compared to R.

     If the resistance of the switches isn't small compared to R, then it would add its resistance to R and creates undesired effects on the Voltage output.

 

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