Lab 5 - EE 421L 

Authored by Charlie Torres-Garcia 

torresga@unlv.nevada.edu

10/4/2016

Digital Integrated Circuit Design -
Design, layout, and simulation of a CMOS inverter
 
Pre-lab:

Files are backed up in (Drive and Laptop)

Go over Tutorial 4 create NAND.

Lab 6 covers the design, layout, and simulation of NAND, XOR gates and full-adder.

All gates where DRC and LVS and sim using symbols created by the schematics.

Directions for creating NAND/XOR

• Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
• Create layout and symbol views for these gates showing that the cells DRC and LVS without errors
• ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol  
• ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
• use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
• ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1

NAND

Schematic:                                                                      Symbol:

        
Layout:                               Extraction:
      
DRC:                                                                                                     LVS:
   

XOR

Schematic:                                                                                Symbol:

  

Layout:                                                                                                        Extraction:
   
DRC:                                                                                                         LVS:
   


Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11).

Now we create a schematic to simulate the logic operations of our gates (NAND/XOR/INVERTER)

Using the following settings to simulate the Logic operations (Truth Table).

SIM results:                                                                                                             Created a Truth table with this results    

• Using these gates, draft the schematic of the full adder
• Create a symbol for this full-adder
• Simulate, using Spectre, the operation of the full-adder using the symbol

Schematic using Symbol:

SIM results of Full-Adder:

• Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
• full-adder inputs and outputs can be on metal2 but not metal3
• DRC and LVS your full adder design
  

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