Project
For the first part of the project
we had to create a detector that detected a sequence of numbers. The sequence
given to us was 101011.
We start off by creating a
transmission gate. The transmission gate consists of one PMOS and one NMOS. The
transmission gate will be used in the construction of the D Flip Flop.
Figure 1
Figure 2
For our D Flip Flop we will also
be using inverters. For this we can bring back our 12u/6u inverters from the
previous labs.
Figure 3
Now we construct the D Flip Flop.
As seen below we create the schematic using transmission gates and inverters. On
the transmission gates we will be putting our clock and clock compliment.
Figure 4
Figure 5
Now that we have derived the
schematic and symbol, we should test it to see that it works properly before
moving on. As seen below we test the Flip Flop and achieve successful
simulations.
Figure 6
Figure 7
Now that the D Flip Flop has
successfully been constructed and tested, we need another component for our
detector. We need to build a 6 input NAND gate for our 6-bit sequence. Below we
see that for the schematic we put 6 PMOS in parallel and 6 NMOS in series for
out 6 input NAND.
Figure 8
Figure 9
Now that we have all our
components for the detector, we can start to build it. 6 D Flip Flops will be
used, one for each bit of the sequence. Below is the full detector circuit and
successful simulation.
Figure 10
Once the wanted sequence, 101011,
has fully gone through, the detector responds accordingly and detects the
wanted value.
Figure 11
Next part of this is to layout
the design.
We begin by laying out the
transmission gate. Seen below is a layout for the transmission gate using
12u/.6u PMOS and 6u/.6u NMOS.
Figure 12
Figure 13
Figure 14
Figure 15
Now I begin to layout the 6 input
NAND gate. The inputs are labeled A-F and the output will be Z. The NAND gate
can be seen below
Figure 16
Figure 17
Figure 18
Figure 19
The inverter used in this project
is from previous labs. It consists of a 12u/.6u PMOS and 6u/.6u NMOS.
Figure 20
From this now we can construct
the D-FlipFlop. The schematic can be referenced at figure( ). Below is the D-FlipFlop
with successful DRC and LVS.
Figure 21
Figure 22
Figure 23
Figure 24
To make sure that the D-FlopFlop had been laid out properly, I ran a simulation to
check that it was outputting its proper function. And as it can be seen below
that the D-FlipFlop is working properly.
Figure 25
Now that all the parts necessary
for the detector have been laid out, we can begin to construct our detector.
Below is the layout for the schematic with labels of parts.
Figure 26
Below is the layout to show where
the pins are for the D, clk, and Detect(output)
Figure 27
Successful DRC and LVS
Figure 28
Figure 29
Figure 30
After laying out the detector, I
ran an extracted simulation to make sure the design was correct and work
properly. It can be observed below that the layout design does work properly
showing that the detector turns on rising edge once the 101011 output has been
detected.
Figure 31
Also it can be seen that when the
detector is input with any other sequence, for example 001011, the detector is
not turned on.
Figure 32
A requirement for this project is
to add a buffer at the output of the buffer. Below is shown the 4 stage buffer
that was used. This buffer will be used to smoothen out our signal that will be
output from the detector.
Figure 33
Figure 34
Figure 35
Figure 36
The layout for the detector with
the buffer is seen below. The layout is exactly the same as before except now
we have included a 4-stage buffer.
Figure 37
Also now the detect pin is
located on the output of the buffer rather than the inverter.
Figure 38
Figure 39
Figure 40
Simulation of detector with
buffer.
Figure 41