Lab 6 - ECE 421L
Prelab:
Pre-lab work
- Back-up all of your work from the lab and the course.
- Read through the lab in its entirety before starting
to work on it
______________________________________________________________
Lab:
To begin we constructed a 2-input
NAND gate and a 2-input XOR gate which consisted of MOSFETS that were 6u/0.6u.
First we start constructing an
inverter
Below is the schematic for the
inverter
Figure 1
From the schematic we can create
a symbol that we will be used later on
Figure 2
Now we can begin to lay out our
inverter
Figure 3
Figure 4
After laying out our inverter, we
extract our design and then LVS it to make sure it matches our original
schematic. You can see below that the LVS was successful
Figure 5
Figure 6
Next step is to construct a NAND
gate. We will use the inverter schematic in the building of the NAND gate along
with another PMOS and NMOS.
\
Figure 7
From the NAND schematic we derive
a symbol
Figure 8
Now we begin to lay out our
design and DRC it to make sure we do not have any errors. As seen it passes the
DRC with 0 errors
Figure 9
Figure 10
Extract the layout and LVS it to
make sure the layout matches the schematic of the NAND.
Figure 11
Figure 12
The next experiment is to
construct a XOR gate. We use the inverter once again in our schematic of the
XOR. On our inverters we put no connection pins so that they do not be counted
as floating.
Figure 13
Symbol for XOR
Figure 14
Next the layout of the XOR and DRC
to make sure there are no errors. As seen below there were no errors
All the PMOS devices are
connected to the vdd! And all the NMOS are connected to the gnd!
In this layout we use metal 2
along with poly and metal 1 because since there are so many connections it is
easier to jump the connections.
Figure 15
Figure 16
We extract our layout and LVS to
match with the schematic. Below is the matched LVS
Figure 17
Figure 18
Since all the gates for the Full
Adder are created, we can test out the logic
|
A |
B |
NOT A |
NAND |
XOR |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
|
1 |
1 |
0 |
0 |
0 |
Figure 19
As seen below all gates seem to
be working properly. If you look closely thee is a slight glitch in the XOR
gate. Reason for this could be since many gates have different delays, rise
times, fall times, and other significant perimeters.
Figure 20
The final experiment is to begin
constructing the Full Adder. In this Full Adder we will use 3 NAND gates and 2
XOR gates.
We can begin building our
schematic using the symbols we created earlier
Figure 21
We then derive our symbol from
the schematic
Figure 22
Before moving on I did a
simulation on the Full adder using the symbol to see what I can expect from my
layout and be able to cross check my results. There were voltage sources
connected to input a, b, and cin. Then cout and s are the outputs.
Figure 23
The logic we expect to see is
|
a |
b |
cin |
s |
cout |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
1 |
0 |
|
0 |
1 |
0 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
|
1 |
0 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
|
1 |
1 |
0 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
The result from the schematic
above is seen below
Figure 24
Now we can begin to layout the
Full Adder. In the layout of this full adder there was metal 3 used as well.
DRC as well to check for any possible errors
Figure 25
Figure 26
Then the extracted view is used
to LVS with the schematic to ensure that all went well in the layout of our
Full Adder. As seen below all net-lists matched
Figure 27
Figure 28
After everything we can now
simulate our extracted view and see if our results match with the simulation from
the symbol. And as you can see the results are the same from the extracted as
they were from the schematic simulation. Once again we see that there is a
glitch in the XOR.
Figure 29