Lab 4 - ECE 421L
Prelab:
Pre-lab work
- Back-up all of your work from the lab and the course.
- Read through this lab before starting it.
- Go through
Tutorial 2 seen here. - In the simulations in this lab the body of all NMOS
devices (the substrate) should be at ground (gnd!) and the body of all
PMOS devices (the n-well) should be at a vdd! of 5V.
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Lab:
In this lab we had to basically
do tutorial 2. Tutorial 2 taught us how to make our NMOS and PMOS. Once we did
tutorial 2 we were able to copy our files from there and use them for this lab.
The first part was to make an
NMOS. It had four terminals which were drain, source, gate, and ground. Once
the NMOS was built we then created a symbol for it. The width was set to 6μm and the length was set to 600nm.
Figure 1
Figure 2
Then we use the symbol and
instantiate it into our schematic where we will be attaching voltage sources to
it.
V0 is set to VGS
VDS is set to 0V
Figure 3
Seen in the simulation below is 
where VGS goes from 0 to 5V in 1V increments. VDS goes from
0 to 5V as well, but in increments of 1mV.
Figure 4
The second part was the same 
vs. VDS, but this
time we changed VDS to be 100mV and it went from 0 to 2V with increments of
1mV.
Figure 5
After finishing the NMOS with all
the simulations, the next thing was to do the same process of constructing and
simulating, but with a PMOS.
Once again we start with
constructing the schematic and then creating the symbol for it. For the PMOS we
had four terminals which are drain, source, gate, and vdd. The width was set to
12μm and the length was set to 600nm.
Figure 6
Figure 7
Then the symbol we created was
instantiated into the schematic below. In the schematic you can observe there
are three voltage sources.
V0 is set to VSG
VSD is set to 0V
V2 is set to 5V
Figure 8
Seen in the simulation below is 
where VSG goes from 0 to 5V in 1V increments. VSD goes from
0 to 5V as well, but in increments of 1mV.
Figure 9
The second part was the same vs. VDS, but this
time we changed VDS to be 100mV and it went from 0 to 2V with increments of
1mV.
Figure 10
After we have built our NMOS and
PMOS, we can begin to work with the layout so that we can DRC and extract it.
Below is the NMOS we are given
which we attached a ground to and added pins for our G, S, D.
Figure 11
Then attached are pads to each
terminal
Figure 12
Now we can DRC our layout to see
if we have any errors or warnings, but as you can see it was good and passed
the DRC
Figure 13
From there we are able to extract
our NMOS and see all the values and all four terminals with our pins
Figure 14
Now that we have extracted our
NMOS with pads, we can run our LVS and match the extracted with our original
schematic
Figure 15
Below is the symbol created for
NMOS with four pads attached to the terminals
Figure 16
Next we have to do the same with
PMOS. We must layout our design and then go through the process to get our LVS
to show that our design matches and works.
Below you can observe the given
PMOS
Figure 17
Just like we did with the NMOS,
we attach four pads to each terminal of the PMOS
Figure 18
Run a DRC for PMOS to see if we
did anything wrong, but as expected no errors
Figure 19
Extracted view shows us our PMOS
with our pins and terminals we set
Figure 20
From our extracted view we begin
and run a LVS which shows that our netlists do match
Figure 21
Below is the symbol that was
created for the PMOS with the four pads attached to each terminal
Figure 22