Lab 3 - ECE 421L

 

Authored by Raheel Sadiq,

sadiqr@unlv.nevada.edu

September 21st, 2016

 

 

 

 

Prelab:

 

 

 

 

 

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Lab:

 

In this lab we began with copying our 10k n-well resistor we created in tutorial 1. The length and width for the resistor were calculated using a 12.5 lambda to dictate the ratio.

 

ntap

Figure 1

 

 

With the length and width determined above, we can build our resistor and resistor value needed for our N-well resistor is 10k and as it can be seen when the n-well is extracted the value of the resistor comes out to 10.21k ohms.

 

closeup

Figure 2

 

 

After our resistor has been build and confirmed for the value wanted, we can start building our DAC. Our DAC is build using our N-well resistors which will replicated the schematic below. The N-well resistors are laid out in series and parallel just like the schematic below.

 

image001

Figure 3

 

 

Each resistor is laid out in parallel and series just like how our schematic we used for our tutorial 1. Each pin can also be seen being assigned the same exact way it was in our schematic going from b0 to b9.

 

ParallelSeries

Figure 4

 

 

Finally we had to put the DAC through simulations and confirm the design works. The first simulation is to DRC the design.

 

DRC

Figure 5

 

 

Next we extract our layout. Extracting it shows us how the values of each resistor come out.

 

extracted

Figure 6

 

 

Once the DRC shows no errors and we have extracted our layout, we can run an LVS to confirm our netlists match and as you can see they do match which means our design is good.

 

LVS

Figure 7

 

 

The netlists matched as shown in the image below

 

netlist

Figure 8

 

 

Simulations:

 

First simulation is from the ideal DAC with the ADC schematic. You can observe that both input and output are on top of each other.

schematicsim

Figure 9

 

 

Simulation below is from the DAC when all pins are set to ground except for pin 9. Also there is a 10pF load on the output.

 

secondsim

Figure 10

 

 

Third simulation is for the DAC and ADC schematic with a 10k ohms load.

 

thirdsim

Figure 11

 

 

Fourth simulation is the same DAC and ADC schematic except the 10k ohms load is switched out for a 10pF load.

 

fourthsim

Figure 12

 

 

Last simulation is the same schematic with DAC and ADC except now the 10k ohms resistor and 10pF capacitor are set in parallel on the output.

 

fifthsim

 

 

 

 

 

lab3 folder

 

 

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