Lab 2 - ECE 421L
Prelab:
For the prelab we had to download the lab2.zip folder which
contained examples of the ADC and DAC. Next step was to unzip the downloaded
file and add it to the cds.lib. sim_Ideal_ADC_DAC was used for our schematic
that will be used in the postlab as well.
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LAB 2:
In this lab we
had to design a 10-bit DAC using an n-well resistor. We began with creating a
large circuit with resistors in parallel and series as
Figure 1
Next step was to turn our
schematic into a DAC symbol. The reason for turning out schematic into a symbol
is to make our lives easier. Turning it into a symbol helps us picture what is
going on with the pins without the whole schematic being there to confuse us
with so much going on. It's all for simplification.
Figure 2
Next was to
implement our symbol into the schematic we were given. We got rid of the DAC
that was given to us and replaced it with the DAC that we created ourselves.
This image is the given DAC which will be
replaced with our own created DAC.
Figure3
Below is where the given DAC was deleted
and the symbol created was put in.
Figure4
The simulation from the ideal ADC attached
to my symbol is shown below
Figure 5
Then there was a load of 10k load added
onto the circuit.
Figure 6
Figure 7
The resistor load was switched out for a
10pF capacitor
Figure 8
Figure 9
After going through the two types of
loads, we then put the 10k resistor and 10pF in parallel. We figure out our 50%
of the signal where the time delay is calculated.
Then the time delay with at 10kΩ resistor 10pF capacitor comes out to be
Figure 10
Figure 11