Lab

Lab Project - ECE 421L

Authored by Billy J. Louis III,

Today's date: 16 November 2016

Louisb2@unlv.nevada.edu

Files that backup this project can be found here.

PART 1:

Lab description: Sequence detector using an AND gate, a Transmission gate,

an inverter, a buffer, and a D-FlipFlop.

Remark: The detector has a 6-bit input and a 1-bit output. The output will be "1" when the sequence of the input is detected.

1. Schematic and symbol of the transmission gate:

2. Symbol and schematic of the Buffer :

simulation of the buffer:

3. AND gate symbol, schematic and simulation's waveform:

Note that the output of an AND gate is "1" if all its inputs are "1" --- and the ouput is "0" if at least 1 input is "0"

4. Edge trigger/D-FlipFlop gate schematic, waveform simulation and symbol:

Note that Qnot is behaving funny, this happened because this flipflop is to be operated at a particular frequency which I have not have a chance to determine.

Using trial and error to set up the parameters of the voltage sources (clock and input ) would fix the problem, by varying the pulses, periods, and time delay of the voltage

sources. Nevertheless, there was no much time left to fix this problem. Hence, I will fix it before part 2.

5. Sequence Detector (Schematic, Symbol and simulation):

The squence is: 101011

Again, the same problem that I have with the FlipFlip occurs, I have not yet figured out how to set up the right frequency which depends on the parameters of the voltage sources. This will be fix when turn in "PART 2" of the project.

I did not have to wait for long to fix the frequency problem that was diccussed earlier. I got the help I needed 8hrs later when I went to class (Lab). Additionally, I had to switch two wires (clk and clk_not) because they were in the wrong place. These wires are located in the clsoest TransGate from the input signal in the EdgeTrig/D-FlipFlop module.

* New D-FlipFlop schematic: