Lab 7 - ECE 421L 

Authored by Billy J. Louis III,

Today's date: 16 November 2016

Louisb2@unlv.nevada.edu

1. Four-bit Inverter & Four-bit nand-gate:

                a. Schematic of the 8-bit inverter and the 8-bit nand-gate (using a 6u/0.6u NMOS and PMOS.) 

                                      b. Simple Simulation of a 4 - bit inverter:

2. NOR gate Schematic and symbol (8 bits) & OR gate schematic and symbol (8 bits):

3. AND gate Schematic and Symbol (8-bit):

4.  Miscellaneous: (some simulation for the above components)

          a. OR gate simulation: (notice that the lower the value of the capacitors the better the waveform -> lower value: less time for the capacitor to charge and discharge)

                     b. AND gate simulation:

5.  Multiplexer Symbol and waveform (2-bit):

6. MUX Schematic,  simulation and Symbol (8-bit):

note1: when S = 1, Z = A

note2: when S = 0, Z = B

7. DEMUX Schematic, Symbol and Simulation (2-bit):

8. DEMUX Schematic, Symbol and Simulation  (8-bit):

9. Full Adder (1 bit): 

                  a. Symbol and Schematic:

                        b. Layout, LVS check and Extracted view:

10. Full Adder (8-bit):

                                a. Schematic, Symbol and simulation:

                                        b. Layout and Extracted View:

                       c. DRC and LVS chech:

       NOTE: the LVS failed to match but I cannot figure out why, the LVS/si.out file shows unmatched = "0". I am not sure how to fix that (yet).