Lab 6 - ECE 421L 

Authored by Billy J. Louis III

louisb2@unlv.nevada.edu

Today's date: 12 October 2016 

  

Lab description: Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

             

PRELAB: Go through Tutorial 4 & BackUp Files - As usual, I only do Computer/Hardrive backups, No online storage.

              Save everything on the school computer then transfer everything to my laptop via thumbdrive, then

              smash the thumb drive with a pneumatic jackhammer. At the end of the month all files will be saved

              on a hardrive. 

             This hardrive will then put back inside an empty and unused microwave oven which protect

              the hardrive from any solar flares or electromagnetic out burst. You don't believe me? disconnect your microwave

              oven and put your cellphone in it, try to call it with someone else's phone - the signal will not go through.

12_Backup.PNG

                       

POSTLAB:

1. Draft the schematics of a 2-input NAND gate and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

Create layout and symbol views for these gates showing that the cells DRC and LVS without errors.

           Part A:

Schematic - Symbol & Extracted view of the a 2 input NAND gate:

3_SymbolSchemExtracred.PNG

                    

Layout - DRC check and LVS check:

3_layoutDRC_LVS.PNG

                

The Symbol is being renamed in the following image:

4_nandRenamed.PNG

         

The NAND gate Simulation After watching Tutorial 4 (video):

2_nandSimulation.PNG

           

                    Part B:

Schematic - Symbol ot the 2 inputs XOR gate :

8_symbol_&_Schem.PNG

           

Layout - DRC and LVS test of the 2 inputs XOR gate:

I might have wasted about 0.3 um space length because I did not merge the actives of the PMOS (2 & 3) and PMOS (4 & 5)

I could not figure out how to remove the metal (metal1) from the active area. The process showed in the tutorial does not work for me.

Layout_metalDelete.PNG

6_layoutXOR.PNG      

           

Etracted View of the 2 inputs XOR gate:

7_extracted.PNG

             

             

2. Simulation of the inverter, the 2 inputs NAND gate and the 2 inputs XOR gate:

I felt a lot of pain setting the right parameters for the voltage sources because I wanted the waveform to be glitches free, but, it finally turn out to be perfect.

I just cannot say the same for the waveform of the Full_Adder.

8_symbol_Simulation_NANDxorNOT.PNG

The values of the waveform reflect the ones of the following table:
 A -----------------   TRUTH TABLE -------------------- B      OUTPUT
INVERTER    0                                                                                  N/A                 1
    1                                                                                  N/A                 0
A NAND B    0     [(A*B)' = A' + B' = 0' + 0' = 1 + 1 = 1]                   0                 1
    0                                                                                     1                 1
    1                                                                                     0                 1
    1                                                                                     1                 0
A XOR B    0     [ (A'B)+(AB') = (0'*0)+(0*0') = 0]                          0                 0
    0                                                                                     1                 1
    1                                                                                     0                 1
    1                                                                                     1                 0

                             

 3. Full_Adder: 

                     a. Symbol and simulation: I have been having a hard time eliminating all the glitches, thus, producing an outcome that reflects the table 100% seems very hard. 

9_FullAdder_SimulationSymbol.PNG

                            

                       b. Schematic of the Full_Adder

9_FullAdder_SchemSymbol.PNG

                                    

                        c. Layout and Extracted view of the Full_Adder:

10_FullAdderLayout.PNG

10_FullAdderExtracted.PNG

                                                        

                 d. DRC and LVS test for the Full_Adder:

11_FullAdderLVS_DRC.PNG

                

           

Lab6 Zipfile: Here

Lab6 Cadence File: Lab6_BJL.rar

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