Lab 5 - ECE 421L 

Authored by Billy J. Louis III

Louisb2@unlv.nevada.edu

Today's date : 05 October 2016

 PRElab: Backup file: 

I do not use online storage, ever. Especially because the internet is given away to Iran,Russia and 

other foreign countries. Hence, I use hardrive to store my files where I bacKup my Computer every

month. For more information on the internet subject being taking over research the company called ICANN.

POSTLab description: Design, layout, and simulation of a CMOS inverter

Draft schematics, layouts, and symbols for two inverters having sizes of: 

• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4.

 1. Inverter schematic & symbol:with W/L = 12u/6u:

 2. Inverter schematic & symbol:with W/L = 48u/24u:

3. Layout, LVS and DRC of the inverter for M = 1:

4. Layout, LVS and DRC of the inverter for M = 4:

5. Extracted View of both inverters M=1 & M=4 (W/L = 12u/6u & W/L = 48u/24u):

    .

6. Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load

Add a return to the listing of your labs

               a). Inverter M=1: driving a 100fF

                             b). Inverter M=1: driving by a 1pF:

                             c). Inverter M = 1: driving a 10 pF:

                            d).Inverter M = 1: driving by a 100pF:

REMARK: The larger the capacitor the longer it takes to discharge, additionally, the smallest capacitor discharges completely before the the pulse switches

from 5v to 0v which gives a curve equal to the input voltage.

                           e). Inverter M = 4: Driving by 100fF:

                           f).Inverter M = 4: Driving by 1pF:

                           G). Inverter M =4: driving by a 10pF:

                            h). Inverter M = 4: Driving a 100pF:

REMARK: The larger the capacitor the longer it takes to discharge, additionally, the smallest capacitor discharges completely before the the pulse switches

from 5v to 0v which gives a curve equal to the input voltage.

7.  Both inverters Pass the Cadence's Ultrasim:

The simulation are showned for only The inverter with M = 1 (100fF) and the inverter with M = 4 (100pF) which are simular to the regular transient simulations:

               a. Image of M1 = 100fF

                        b. Image of M4 = 100pF :

LAB5 ZIPFILE:

Cadence: Lab5 Folder_ : Lab5_BJL.rar

END OF EE421L LAB5: Return to the LAB directory.