Lab 4 - EE 421L 

Carlos Lemus

lemus@unlv.nevada.edu

September 29, 2016

Pre-lab work:

• Back-up all of your previous work from the lab and the course.

• Read through this lab before starting
  

• Go through Tutorial 2

• In the simulation in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at vdd! of 5V
  

Lab Description:

• This lab will include IV characteristics and layout of NMOS and PMOS devices in ON's C5 process.
  

Lab Report should include:

• IV curves of the NMOS and the PMOS.

• The layout of the NMOS and the PMOS.

• Layout of the NMOS and PMOS attached to 4 probe pads
  

NMOS

    The first part of the tutorial was to create an NMOS of 6u/600n schematic and generating a symbol for it to use in the IV curves, making sure that the body of the is gonnected to gnd! (universal ground). Also, use nmos4 instead of just NMOS

PART I

Then we need to connect the NMOS device to voltage sources. We create varying voltages VGS (voltage Gate to Source) and VDS (Voltage Drain to Source).

We typically define the NMOS IV characteristics as ID vs VDS for a fixed VGS.

The first plot of IV curve was the curerent ID vs VDS where VGS varies from 0 to 5V in 1V increments and VDS varies from 0 to 5V in 1mV increments. Below shows the change in current for an incrementing VDS for each differnt step in VGS. We can accomplish this by seeting the a sweeping analysis and a design variable in the ADE L.

PART II

The second IV curve was ID vs VGS where VDS was fixed at 100mV and VGS varies from 0 to 2V in 1mv increments

This waveform is generated by the ID vs VGS. We can see that the mosfet starts to conduct current after VGS > Vth (when the curve increases)

PART III

Now we can do the layout for the NMOS connected to 4 probe pads. We can use the pad and symbol for it created in homework 5.

Now following Tutorial 2 we can layour the NMOS

•     The NMOS consists of:

• Active layer to make a hole in the STI
  

• n-select to make the heavily doped nwells
  

• two metal1 and cc connectors for Source and Drain

• a poly layer conneted to a m1_poly connection for the Gate

• and a seperate ptap for gnd!
  

We DRC they layout and then we LVS with the NMOS schematic used in the NMOS IV curves IV curves.

Then the pads can be connected to the NMOS device. To connect the NMOS device to the pad we must go up all the way to metal 3 using a via  to connect metal 1 to metal2, then via2 to connect to metal 3 for to connect to the probe pad.

Then we can just DRC witout any erorrs\

With the given schematic we can also LVS the system.

PMOS

    Part I

    We will now do the same proccess we did for the NMOS, but for a PMOS starting with the schematic and the symbol
    This time the body will be connected to B

1. First PMOS IV curve will show ID vs VSD where VSG varies from 0 to 5V in 1V increments, and VSD varies from 0 to 5v in 1mV increment
2. The PMOS has a Width of 12 um and a length of 600nm
3. Notice also that Source is not connected to ground because of the PMOS structure where the source needs to be connected to a voltage source to create enough potential for the mostfet to conduct.
   

We get a very similar waveform outpout with the same idea that each different line represents a VSG value




Part II

The second PMOS IV curve was ID vs VSG where VSD was fixed at 100 mV and VSG varies from 0 to 2V in 1mV increments




We also see a similar result to the NMOS




Part III

Finally, we will layout the PMOS device and connected it to pads.

The PMOS consists of :

• A p-active layer
• An N-well (Since we are using a PSubstrate standard)
  
• p-select
• poly1 connected to a m1_poly with a cc connection that will make up the Gate
  
• cc connections from the p-well to metal1 that will be the Source and Drain
• an Ntap with a cc connection to m1 that will be the Body of the PMOS
  

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