Detector - EE 421L

Carlos Lemus

11/16/2016 

The goal of this project was to create a detector that would detect if the sequence 101011 was given and output goes High otherwise it is Low.

To do this, we must create a D Flip FLop to store the sequence as it comes in.

We also create a symbol to reference the D Flip Flop later in our simulations

To actually compare the bits to a sequence we must create a NAND gate of 6 bits. This can be done by adding PMOS'in parallel and NMOS' in series

We also need a symbol for this schematic

The components are put together so that a piece wise function creates our sequence 101011 in reverse order since the last bit will need to go first to reach our last D Flip Flop. A clock is neaded since the D Flip Flops work off a rising edge trigger, meaning when the clock goes high. Then the out put of Q or Qnot is sent to the NAND. We need to send Qnot so that the NAND gate can check if all values are 1. Since NAND will return 0 when all values are true we must invert the output to get the correct value that we have detected the sequence

The image below shows the piecewise function for reference

We are ready to simulate it. Notice the output goes high when

q0 = 1; q1 = 1; q2= is 0 but it shows turning to 1; q3 = 1; q4 = 0 turnin 1; q5 =1. The main point to look at here is that

We begin the layour process of our detector. First, lets copy our simulation schematic into a new detector cell and remove the schematic's power supplies and output and swap with pins accordingly

Next we can create a symbol for the detector. (To be different a batman symbol was used, Batman is a detective)

To make things easier we will break things down. First, we will layout the D-flip-flop, DRC, and LVS

Next, we can layout our NAND 6 input gate, DRC, and LVS

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Our inverter has been layout from previous labs (lab 7) and we can use this

Finally, we put it all together. This can be done by instantiating each layout previously created. The layout below shows the Q and Q' according to the schematic attached to the q0-q5 of the NAND 6-input gate (shown at the very end nex to the inverter) and finally through the inverter to input high when the input is found.

We can simulate the extracted layout. Only the output is shown this time. A 1pf cap was just added to show a cleaned up output, though it will not give full logic levels without buffers after it.

ZIP file of detector

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