Lab 6 - ECE 421L 

Authored by Antanasia Jones

jonesa20@unlv.nevada.edu

10/26/2016 

For this lab we had to create schematics, symbols and layouts of a 2-input NAND, a 2-input XOR gate and a full-adder. Each symbol had to be used in a simulation schematic to make sure it operated the way it was supposed to based on the truth tables.   

For the first part of the lab I created schematics for the 2-input NAND gate and the 2-input XOR gate using 6u/0.6u NMOSs and 6u/0.6u PMOSs. Examples of these gates represented by MOSFETs are found in chapter 12 of the CMOS textbook. I then generate symbols for each gate that coincided with the typical symbol for each gate. Below are images of the schematics and symbols of the the NAND and XOR gates. 

 
                   NAND Gate Schematic                                                               NAND Gate symbol                            

         

                                  XOR Gate Schematic                                                                     XOR Gate Symbol
 

 

         NAND Layout                                                 NAND DRC                                                                       NAND LVS
 

 

                          XOR Layout                                                                    XOR DRC                                                                                           XOR LVS
 

Once these cells were completed a schematic was generated to test the function of each gate including the inverter that was created in lab5.  Using Spectre simulate the operation of the gates were tested for the inputs AB = 00, 01, 10, 11. This was done by having 2 seperate power supplies with pulse inputs ranging from 0 to 5V, where the periods and pulse widths were set to different values, with the period of B being half that of A. Below are truth tables showing the operation of the inverter, the NAND gate and XOR gate along with images of the schematic that was generated with the gates and the simulation results.
 

                   Gate Simulation Schematic                                                                                           Gate Simulation Results 

As seen from the results the gates' operation match that of their respective truth table as expected. It should be noted that there is a glitch in the output for the XOR gate. This occurs due to the input A being on the rising edge and input B being on the falling edge at the same time. The XOR gate sees this as both inputs being off, or having no value, which gives a false input of 0 momentarily until both inputs go their respective vaules.  

For the last part of the lab I drafted a schematic and a layout of a full-adder using the cells for the NAND gate and the XOR gate. A symbol of the schematic was then created to represent the full-adder. The layout of the full-adder was verified to have passsed both DRC and LVS. Below are the images of the full-adder schematic, symbol, layout, DRC and LVS tests. . 

                                             Full-adder Schematic                                                                                 Full-adder Symbol

                                                                                           Full-adder Layout

                                                     Full-adder DRC                                                                                                    Full-adder LVS

The glitches or false outputs given for the results of the full-adder occur for the same reason given above, where two or more inputs are on the falling edge or rising edge at the same time. This results in the output viewing these as being off or having no value and giving an output that coincides with these inputs being 0. 

A zipfile of the cells used in this lab are placed here.