Lab 3 - ECE 421L
In this lab we had to create a layout of our Digital-to-Analog (DAC) converter schematic using n-well resistors and verify that the layout and schematic matched.
To create the layout of the DAC schematic we had to use 10k n-well resistors. The sheet resistance of an n-well in the C5 process according approximately 800 ohms according to MOSIS. Using the standards given by MOSIS that the minimum size of the n-well is 12 lambda (where lambda = 0.3 um). So the minimum width size of the n-well resistor is 3.6 um.In order to not be right on the edge of the minimum value, I chose the minimum value to be 4.5 um, also due to that being the relative size of the n-tap.
R = (800 ohms/square)(L/W) = 10k ohms W=4.5 So, L = 56.25
However, for the layout design to be on the grid the width and length values have to equally divisible by 0.15 um. Even though 56.25 is evenly divisible by 0.15, this value creates a larger resistance than needed so I rounded the number down to 56.1 which produces a better value closer to 10k ohms. Below are images of the n-well resistor and the extracted version showing the resistor value.
Using this 10k n-well resistor, I layed out the resistors (31 in total) in parallel connecting the resistors on the metal 1 layer in the same configuration as the schematic for the DAC making sure to have space between each resistor to avoid DRC violations. Below is an image of the originanl DAC schematic along with the layout of the schematic.
I then extarcted the layout and performed a DRC amd LVS to determine if the rules where followed and if the layout matched the original schematic.
The zip file for lab 3 containing the DAC schematic, layout, and simulations is placed here.