Lab 8: Chip 7 Project - ECE 421L
The design directory can be found here: Chip7_f16.zip
This chip contains:
1 31-stage ring oscillator with a buffer capable of driving an off chip 20pF load
1 NAND gate using 6/0.6 NMOS and PMOSs
1 NOR gate using 6/0.6 NMOS and PMOSs
1 inverter made with a 6u/0.6 NMOS and 12u/0.6u PMOS
1 6u/0.6u 4-terminal PMOS transistor
1 6u/0.6u 4-terminal NMOS transistor
1 25k-10k voltage divider
4 (each group member's) sequence detectors that detect the sequence 101011
Pin Connections
Pin | Component | Considerations | ||
1 | A |
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2 | AnorB | |||
3 | NOR vdd | |||
4 | PMOS G | |||
5 | PMOS D | |||
6 | PMOS B | |||
7 | PMOS S | |||
8 | RS detect out | |||
9 | RS detect vdd | |||
10 | TH detect out | |||
11 | TH detect vdd | |||
12 | ||||
13 | ||||
14 | ||||
15 | NMOS D | |||
16 | NMOS G | |||
17 | NMOS S | |||
18 | 25k (out) / 10k (in) | |||
19 | 25k (in) | |||
20 | ground | |||
21 | TKF Detector vdd | |||
22 | TKF buffout | |||
23 | SM buffout | |||
24 | ||||
25 | ||||
26 | SM Detector vdd | |||
27 | ||||
28 | ||||
29 | ||||
30 | detector inputs | |||
31 | detector clks | |||
32 | ||||
33 | NAND vdd | |||
34 | inverter vdd | |||
35 | Ring Osc OUT | |||
36 | Ring Osc VDD | |||
37 | Inverter OUT | |||
38 | Inverter IN | |||
39 | AnandB | |||
40 | B |
Testing the Chip
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25k Resistor
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25k-10k Voltage Divider
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NAND
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NOR
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Inverter
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Ring Oscillator
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PMOS
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NMOS
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Detectors
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NAND gate with 6/0.6u NMOSs and PMOSs:
NOR gate with 6/0.6u NMOSs and PMOSs:
Inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS:
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Two 20k resistors, one made using n-well and the other using hi-res poly2:
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12u/0.6u PMOS and NMOS devices:
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Padframe: