Lab 7 - ECE 421L 

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Authored by Tyler Huddleston, huddle10@unlv.nevada.edu

10/26/2016

• Back-up all of your work from the lab and the course.
• Go through Tutorial 5 seen.
• Read through the entire lab before starting it.

Schematic

Simulation Schematic

Simulation Results

Schematic

Simulation Schematic

Simulation Results

Schematic

Simulation Schematic

Simulation Results

Schematic

Simulation Schematic

Simulation Results

Schematic

Simulation Schematic

Simulation Results

Schematic

Simulation Schematic

Simulation Results

Schematic

Schematic

Simulation Schematic

Simulation Results When S=0, the output is A. When S=1, the output is B.

Schematic

Schematic

Simulation Schematic

Simulation Results When S=0, the input is sent to A. When S=1, the input is sent to B.

Schematic

Schematic

Layout

Layout Single Section

LVS

DRC

Simulation Results

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