Lab 6 - ECE 421L 

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

Authored by Tyler Huddleston, huddle10@unlv.nevada.edu

10/26/2016

This lab involves constructing and simulating CMOS NAND and XOR gates.  Then, using these gates to construct and simulate a Full-Adder circuit.

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 4.
• Read through the lab in its entirety before starting to work on it
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• Draft the schematics of a 2-input NAND gate, and a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)
• Create layout and symbol views for these gates showing that the cells DRC and LVS without errors
• ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol  
• ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
• use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
• ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1
• 2-input NAND schematic
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• 2-input NAND symbol
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• 2-input NAND layout
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• 2-input NAND DRC
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• 2-input NAND LVS
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• 2-input XOR schematic
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• 2-input XOR symbol
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• 2-input XOR layout
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• 2-input XOR DRC
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• 2-input XOR LVS
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• Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)
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• Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)  
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• comment on how timing of the input pulses can cause glitches in the output of a gate:
• There are small glitches in the gate outputs that occur during the transitions of the inputs due to time delays inside of the gates.  Notice the glitches are bigger in the XOR output, which has a larger layout with more PMOS and NMOS devices.
• Using these gates, draft the schematic of the full adder
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• Create a symbol for this full-adder
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• Simulate, using Spectre, the operation of the full-adder using this symbol  
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• Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
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• full-adder inputs and outputs can be on metal2 but not metal3
• DRC and LVS your full adder design 
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