Lab 3 - ECE 421L 

Authored by Tyler Huddleston, huddle10@unlv.nevada.edu

9/21/2016

  

 

This lab focuses on the layout for the 10-bit DAC I have designed in Lab 2.

Designing the 10K n-well resistor

By our design rules, lamda = 300nm.

The minimum n-well width = 12*lamda = 3.6um.

The sheet resistance of n-well = 800 ohms/square.

 

Choose width of 4.5um, thus

L = (R*W)/(Rsquare) = (10K*4.5um)/(800) = 56.1um,

which is rounded to the nearest 0.15um to algin with the grid and pass the DRC verification.

 

 http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/resistor_size.JPG

L=56.1um, W=4.5um

 

 http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/R_10k.JPG

R = 10K confirmation from extracted view

 

The layout

- Each resistor is laid out in parallel in a stack

- The resistors are each a distance of 5.4um between one another

 

http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/DAC_layout.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/DAC_layout_close.JPG

Close up of the layout pattern.  Notice the pins are on metal1.

 

http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/DAC_DRC.JPG

DRC passed.

 

http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/DAC_LVS.JPG

http://cmosedu.com/jbaker/courses/ee421L/f16/students/huddle10/lab3/DAC_LVS2.JPG

LVS passed.

 

 

Link to my design directory here.

 

  

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