Lab Project - EE 421L
Design the schematic and layout of a 6-bit serial input detector
Design a circuit that takes a serial input and detects (outputs a high signal called detect) the sequence 101011
The inputs to your circuit are clk and in
Make sure that the output of your design, detect, is buffered before connecting to a pad
The zip for this lab containing the cells used can be downloaded here.
This project will involve creating a D-FlipFlop for storing data along with a 6-bit AND gate in order to make a detector.
Since we will be trying to detect a 6-bit sequence, 6 D-FFs will need to be connected to one another with their appropriate
output signals going to the 6-bit AND gate. The AND gate will only output high when it has detected the correct sequence.
Each section of this project is discussed in more detail below.
D-FlipFlop Implementation and symbol
The D-FlipFlop that will be designed is positive edge-triggered. Let's call the four transmission gates from left to right as 1 through 4.
This schematic can be split up into two identical sections, left and right. Since the right section will only allow a signal to pass through
when the clock goes high and this section is connected to our outputs Q and Q_not, the output of the FlipFlop is considered positive
edge-triggered. The transmission gates after the buffers, 2 and 4, will allow the signal in that section to continue to be circulated through
when the other gates are turned off, 1 and 3. The feedback inverters are used to store both the Q and Q_not values. Only one section
would be needed if we wanted a latch but since we want a D-FlipFlop that is positive edge-triggered, we need both sections.
Simulation of Positive Edge-Triggered D-FlipFlop
As we can see in the simulation for our D-FlipFlop, the Q and Q_not outputs only change when the clk value goes high (pos-edge).
6-Bit AND Gate Schematic and Symbol
Simply based on our previously created 2-bit NAND gate this AND gate has 6 PMOS in parallel and 6 NMOS in series with their
respective gates tied to one another. The drain of each PMOS is tied to the top NMOS which will be sent to an inverter before
the output pin to invert the NAND signal to AND.
Simulation of 6-bit AND Gate
To make the simulation of this AND gate as simple as possible. The first 5 bits are all tied high while only the MSB in<5> is being toggled back
and forth. As expected, the output signal and6 will only go high when this final bit in<5> is high as well.
3-Stage Buffer For Output Signal detect
Since the output of our design needs to be buffered before connecting it to a pad, a 3-stage buffer has been created for our detector.
The sizes of the PMOS and NMOS are consistent with those used in every other part of this project. To determine exactly why 3-stages
were used, we will look at the equation below for driving a load. A value of 20pF was given for the buffer for lab 8 so that is the C_load
value that will be used and a gain of 8 has been used in class.
Since we are using a gain of 8, any number of stages will have an odd number of inverters since it will be an even number plus the single
inverter from the first stage. To make sure that our output signal from the buffer is not inverted, an extra inverter is placed on the beginning
of the buffer to fix this.
Simulation of 3-Stage Buffer
There isn't much to show for the output of the buffer other than the fact that the reasoning behind the extra inverter explained above.
The output signal does in fact come out without being inverted so the detect signal is not affected.
Schematic, symbol, and simulation of the sequence detector
The schematic of this detector is fairly simple. The clk signal needs to go to each D-FlipFlop to receive its new value on the positive edge of the clock.
Each output Q for the FlipFlops will go to the input of the next FlipFlop in order to propagate the signal. It can also be seen as shifting each of the values
down the line for every clock cycle, or positive edge. The in signal only goes to the first FlipFlop since the data is being sent in serially. Now in order to
detect the correct signal, the output of each FlipFlop has to be tied up correctly. If we are expecting a 1 from a certain bit, the corresponding FlipFlop will
need its Q value to be tied to the AND gate since the correct sequence will output a 1 for that Q bit. The same will occur when expecting a 0. When a
value of 0 is desired, we will tie the output Q_not from the FlipFlop since that value will be 1 going into the AND gate. Now when the entire sequence
is detected correctly, each bit going into the AND gate will be 1 and the AND gate will only output detect high at that point.
This is the schematic that is used to verify the functionality of our detector. A brief explanation of each simulation is down below.
This simulation inputs the correct sequence immediately as 1010111111111.
The detect signal goes high where expected.
This sequence is sent in as 0110101011111.
It is given to show that random values will not cause a false detection.
The third sequence is just another random sequence 0101011110000.
Once again, the proper sequence is detected.
Finally we have the case where the sequence is sent in twice in a row as 1010111010111.
Notice that both times the sequence is detected correctly.
Sequence Detector
For the final layout, the second picture below is a zoomed image of a single FlipFlop (which is first in line connected to in) so that almost every
connection used can be seen a little more clearly. The clk is connected through metal2 to each FlipFlop while metal1 was mainly used for connection
to the 6-bit AND gate, although some metal2 was still required. Every pin is still connected by metal1 though (in, clk, and detect).
