Lab 7 - EE 421L

 

Using buses and arrays in the design of word inverters, muxes, and high-speed adders

Michael Ghisilieri

ghisilie@unlv.nevada.edu

11/9/16

  

  

Lab Work:

  

This lab will cover the 8-bit design of some of the designs introduced in Lab 6 as well as additional

logic gates and devices that will be implemented here. Only one layout will be done throughout this lab,

which is the 8-bit full-adder at the end. The rest will only include simulations and verification of schematics,

mainly including busses.

 

The zip for this lab containing the cells used can be downloaded here.

 

Simulate a 4-bit inverter and show how a capacitive load influences the delay and rise/fall times.

 

As we can see from the simulation below, when an inverter isn't driving a load (out<0>), there is no trouble

outputting the signal correctly and the output wave will look as close to the input as possible. Now as we increase

the load that is to be driven by an inverter, we can see the signal start to lose its shape. out<3> has the smallest

capacitor to drive and out<1> has the largest. With a larger capacitance, the inverter doesn't have enough time

to charge it and the rising edge of the output signal will not be instantaneous.

 

4bit_inverter_sch.jpg

4bit_inverter_sim.jpg

 

 

Create schematics for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.

Provide a few simulation examples using these gates.

 

NAND GATE 

 

nand2_sch.jpg

 

NOR GATE

 

nor2_sch.jpg

 

AND GATE

 

and2_sch.jpg

 

INVERTER

 

inverter_sch.jpg

 

OR GATE

 

or2_sch.jpg

 

 

Create symbols and provide a few simulation examples using these gates.

 

8bit_gates_sch.jpg

 

The truth table for each of the 5 gates is combined in the table below. Two simulations were done on a single

bit of the output of each of the gates, one driving a 100f capacitor and the other with no load. As we can see,

the output signals are similar to that of the 4-bit inverter with the gates driving loads showing less of an accurate

output while those with no load have a more pulse-like output.

 

gates_table.jpg

 

8bit_gates_capload_sim.jpg

 

8bit_gates_noconn_sim.jpg

 

 

Create the schematic for the 2-to-1 DEMUX/MUX with an inverter in your design so the cell only needs one select input S.

The complement, Si, is generated using an inverter.

 
mux_demux_sch.jpg
 
 
Simulate the operation of the 2-to-1 DEMUX/MUX.
 
sim_mux_sch.jpg
 
For the MUX simulation shown below, when the value of S is 0, output Z will get the signal from B otherwise when
the value of S goes to 1, the output Z will get the signal from A.
 
mux_sim.jpg
 
sim_demux_sch.jpg
 
The DEMUX uses a similar concept but now A or B will be grabbing/outputting the signal that Z has based on the
value of S. As we can see based on the sim, A will output the signal from Z when S is 1 otherwise B will output
the signal of Z when S is 0.

 
demux_sim.jpg
 
 
Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
 
8bit_mux_demux_sch.jpg8bit_mux_demux_sym.jpg
 
 
Use simulations to verify the operation of your design.
 
8bit_mux_sch.jpg
 
The sim of the 8-bit MUX will show 4 different outputs (1, 3, 5, and 7) but there is only one image below since outputs
1 and 3 will be the same as 5 and 7, which can be seen here if desired. The operation of each bit is obviously the same
as a single bit with S=0 making Z=B and S=1 making Z=A.

 
8bit_mux_1and5_sim.jpg
 
8bit_demux_sch.jpg
 
The sim of the 8-bit DEMUX will also show 4 outputs (1, 3, 5, and 7) but there is only one image below since outputs
1 and 3 will be the same as 5 and 7, which can be viewed here if desired. The operation of each bit is exactly the same
as a single bit with S=0 making B=Z and S=1 making A=Z.

 
8bit_demux_1and5_sim.jpg
 
 
Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
 
full_adder_sch.jpg

 

 

Create an adder symbol for this circuit.

 

full_adder_sym.jpg

 

 

Use this symbol to draft an 8-bit adder schematic.

  

8bit_adder_sch.jpg

 

 

Using the symbol, simulalte the operation of your 8-bit adder.

 

sim_8bit_adder_sch.jpg

 

As seen from the circuit above the values of the input and output of the full-adder will be (LSB is the leftmost bit):

 

A:        00101101

B:        00011011

Cin:     1

S:        10110001

Cout:                   1

 

The output can be verified with the simulation found below.

 

sim_8bit_adder_sim.jpg

 

 

Lay out this 8-bit adder cell.

Show that your layout DRCs and LVSs correctly.

 

Since the layout of the 8-bit adder is huge, and to give a better look at each bit, here is an image of the 1-bit adder after it was DRC'd and LVS'd.

 

full_adder_lay.JPG

 

Here is the complete layout of the 8-bit adder. The pin names were make extra large to easily see the inputs and outputs of the layout. The DRC of this

layout passed with zero errors as it should.

 

8bit_adder_lay_drc.jpg

 

Finally we have the LVS of the layout with a single bit of the full-adder shown in the background as an extracted view. Once again, as we would

expect (or hope) the LVS passes without error and the net-list matches our schematic!

 

8bit_adder_ext_lvs.jpg

 

 

 

 

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