Lab 5 - EE 421L

Design, layout, and simulation of a CMOS inverter

Michael Ghisilieri

ghisilie@unlv.nevada.edu

9/28/16

Lab Work:

This lab covers the simulation of two CMOS inverters with separate values, the second with

the width of the PMOS and NMOS devices being multiplied by 4. The schematics, layouts, and

symbols of these two inverters will be created before placing them into a circuit for simulations.

A new simulator will be introduced/used in this lab, which is the UltraSim simulator.

The zip for this lab containing the cells used can be downloaded here.

Draft schematics, layouts, and symbols for two inverters having sizes of:

12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u) 

Schematic of the 12u/6u inverter with the symbol view on the right.

Layout of the 12u/6u inverter with LVS that has passed for our first design of the lab.

48u/24u where the devices use a multiplier, M = 4

Schematic of the 48u/24u inverter with the symbol view on the right.

Here is the second layout of the inverter with a multiplier of 4. Once again, we can see that the layout does in fact pass LVS.

Using SPICE simulate the operation of both of your inverters showing each driving a 100fF, 1pF, 10pF, and 100pF capacitive load 

Use UltraSim and repeat the simulations done with spectre.

12u/6u inverter:

This is the final schematic that was used to simulate in both the specre and UltraSim simulators. The vdd is set in the Setup > Stimuli

menu as a global source for the inverter. Note that the capacitor will be used as a design variable to sweep the value of this capacitor

so that we can fit all four of the load outputs on one graph.

These are the settings that were used in the parametric analysis in order to sweep across the 4 values.

It starts at a value of 100fF, steps to 1pF, 10pF, and finally 100pF. This can be confirmed in the simulations coming up.

Just to ensure that we know how to select the simulator in the ADE, here is an image of the

Setup > Simulator/Directory/Host menu where the UltraSim is selected for our second set of simulations.

Comment, in your report, on the results

Plotting all 4 outputs of the inverter on one graph not only makes it easier to compare with the other values

being swept, but also significantly reduces the amount of images that needed to be taken of the simulations.

The first graph shown below is the simulation using specre while the second graph uses UltraSim. It can now

be seen that the four values of the capacitor being plotted are in fact 100fF (1e-13), 1pF (1e-12), 10 pF (1e-11),

and 100 pF (1e-10). The larger the capacitor becomes that needs to be drove by the inverter, the harder it gets

for the inverter to actually drive the load. It becomes apparent around 10pF that the inverter is already having

trouble charging the capacitor. At 100pF it is even worse and the capacitor cannot even discharge.

48u/24u inverter:

Here is the final schematic for our inverter with widths multiplied by 4. The specre and UltraSim simulations were both

done with this schematic. The same parameters and steps were taken as was done with the first inverter, including setting

vdd to a global source and the capacitor to a design variable in order to sweep all four values of the capacitor in one simulation.

 

 
 

 

 

 

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