Lab 3 - EE 421L
Layout of a 10-bit digital-to-analog converter (DAC)
This lab covers the layout process of our 10-bit DAC design as well as some information as to calculating the
values required in order to make the 10k resistor used in our layout. It will show our final, stacked layout and
some simulations will be shown using the extracted view rather than the schematic view.
The zip for this lab containing the layout and other cells can be downloaded here.
Layout a 10k resistor:
Discuss how to select the width and length of the resistor by referencing the process information from MOSIS.
Based on the information provided from MOSIS, the sheet resistance given to us for n-well in the C5 process
is about 800 ohms. The minimum width that our resistor can be is 3.6 microns and grid will snap to .15 microns.
Since Tutorial 1 uses a width of 4.5 microns for the width of a 10k resistor, I decided to stick with that width and
base the length off of that. The length of the resistor can be calculated using the formula given below.
Discuss how the width and length of the resistor are measured.
Layout, DRC, LVS, and extracted layout:
Although no pin names can be seen when the layout is sized to fit, this is what the entire stacked layout looks like.
Here are two zoomed in images of the layout. The left is in layout view while the right shows what the same portion
of the layout will appear as in its extracted view.
Before getting to an extracted view though, we must first DRC the layout and to our luck it has zero errors!
After the DRC checks out and we have extracted our layout, it is time to LVS our design.
The schematic and extracted views are a match and we get the message below after hitting
the run option in our LVS window.
Simulations using extracted view:
In order to use our extracted circuit, we must make sure that it is searched for before the schematic by going
into the Setup > Environment menu of ADE L and placing "extracted" before schematic in the Switch View List line.
After that adjustment has been made, we can run our simulation with the extracted view. I decided to run the
default simulation that was used in the initial Lab 2 similation where we tested the ideal_ADC_DAC. Just to make
sure that our simulation used the extracted view. We can go into Simulations > Netlist > Display to bring up the window
on the left and see that my_10-bit_DAC is using the extracted view. The simulation also looks as it should with a
digital output of 0-5V.
Just to show another simulation using the extracted view I went ahead and drove a 10k resistor load, that we discussed
in Lab 2, that will simply be a voltage divider and cut our output in half from 0-2.5V.
