Lab 2 - EE 421L

Design of a 10-bit digital-to-analog converter (DAC)

Michael Ghisilieri

ghisilie@unlv.nevada.edu

9/6/16

Pre-Lab:

The pre-lab for Lab 2 covers setting up of a library which contains the ADC and DAC that

will be simulated and used to also expand our knowledge of the simulation tools in Cadence.

1) Narrative of the steps from the pre-lab

The first thing to do is unzip our lab2.zip file to our working directory which can be seen in our CMOSedu folder.

After our new folder, lab2, is in our working directory and the path has been added to the .cdsinit file,

we will be able to view the library and the cells within it in our Library Manager window. The file we will

be opening is the schematic of the cell sim_Ideal_ADC_DAC.

Schematic of sim_Ideal_ADC_DAC.

Our initial simulation of the ADC-to-DAC provides a simple graph with input and output going from 0-5V,

but the background color, line type, and line thickness were all changed to show our understanding of the

simulation tools Cadence has to offer.

2) Provide and discuss different simulation results of the ADC and DAC

Changing the input voltage of the ADC to 1.5V amplitude and 1.5V offset along with a different frequency

of 1MHz will cause the input and output voltages to go from 0-3V rather than 0-5V. The period will also be

twice as long as a 2MHz frequency with a 1 microsecond period as shown below.

3) Explain how the LSB of the ADCs input will work

The lab gives the equation 1 LSB = VDD/2^(# of bits) for determining the minimum voltage needed to change

the LSB bit of the ADC. For our ADC, a VDD of 5V is given and it is 10-bits. This gives 5V/1024 or roughly 4.88mV.

Based on this value, anything less than 4.88mV should not cause the ADC to trigger the LSB while anything above

will lead to an output from the DAC that is non-zero.

Setting the input voltage to 1mV, which is less than the minimum 4.88mV needed to change the LSB, will not

cause any of the bits to change and an output of zero should be expected from the Vout trace.

If we now give an input voltage of 5mV, it should be enough to change the LSB and cause a non-zero output.

Lab Work:

The post-lab will cover the creation of a 10-bit DAC while using symbols to simplify the schematic views and make
it easier to put together. Various simulations will be run to verify that the DAC works properly and to answer questions
regarding the DAC.
 
Design of a 10-bit DAC using R of 10k:
 
The 10-bit DAC will be created using 10k resistors with the 2R resistor being split up into two separate 10k resistors.
A single bit of the DAC will look like the schematic below with the symbol view of it shown on the right.
 

 
 
The full schematic of the 10-bit DAC will simply make use of the 1-bit DAC created above but layered on top
of one another with bits 9 down to 0 as inputs and Vout as the only output in the schematic.
 

 
 
Creating a symbol view based on Ideal_10-bit_DAC symbol:
 
To create the symbol view of our own 10-bit DAC in place of the given Ideal_10-bit_DAC symbol, we will need
to navigate in our Schematic Editor to Create > Cellview > From Cellview as shown.
 

 
 
The following menu will now open and after pressing OK, the location of the pins can be changed as well
as their name if desired (that window is not shown below).
 

 
 
Once our symbol has been created, we can delete any unnecessary labels or boxes around our symbol while
just leaving the input and output pin names along with a helpful symbol name (10-bit_DAC in my case).
 

 
 
Simulation of DAC to verify that is functions correctly:
 
Now that we have created the symbol for our DAC, the Ideal_10-bit_DAC can be removed from the
sim_Ideal_ADC_DAC (a copy should be made of this) schematic and replaced with our own. The VDD
and GND pins will be removed but since our symbol is identical otherwise, it can be easily dropped in.
 
 
 
 
This is the output of the simulation using my 10-bit DAC. It is very similar to the output given by the Ideal DAC.
 

 
 
Determining the output resistance of the DAC:
 

 
 
DAC driving 3 different loads:
 
Explain what happens if the DAC drives a 10k load?
 
The first load that the DAC will drive is a resistor of 10K. Since the output resistance of the DAC is already equal to
10K and we are adding a 10K resistor in parallel, it will create a voltage divider where the output from the DAC will be
equal to roughly half of the input voltage. This proves to be true based on the simulation below.
 


 
 
The second load is a capacitor which will have a value of 1pF.
 


 
 
The third load is both a capacitor and resistor which I followed the schematic shown in the lab (Figure 30.14).
 


 
 
Delay and driving a load:
 
This part of the lab involves grounding all of the inputs of the DAC except for the MSB B9. A pulse wave is then
fed into as the input and a 10pF load is driven where we need to predict the delay using 0.7RC. As mentioned earlier,
our R value will be 10K and C will simply be the load of 10pF.
 
0.7RC = 0.7(10K*10pF) = 70nS
I added a 50nS delay to the pulse in this circuit so the delay in the simulation will be 120nS for 1/2*Vmax rather than 70ns.
 


 
   
In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).
Discuss what happens if the resistance of the switches isn't small compared to R.

If the switches offer a large resistance compared to R, then the equivalent resistance will be much less than R
since the continuous parallel resistors of a large resistance and 2R will continue to get smaller. This will cause
the RC value to go down which will decrease the time delay.
 
 

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