Project - EE 421L
Digital Integrated Circuit Design
Authored by James Garner
Garnerj5@unlv.nevada.edu
1 November 2016
Return to: J.Garner EE421 Labs
Project: Design a circuit
that takes a serial input and detects (outputs a high logic signal called
detect) the sequence 101011. The inputs to your circuit are clk
and in. Make sure that the output of your design, detect, is buffered before
connecting to a pad.
We must use the following circuit in order to implement a D Flip
Flop. I created this circuit as a symbol so that it would make creating the D
Flip Flop easier. For creation purposes I called this circuit “Clock_Transition”
Schematic
Symbol
Layout
DRC
LVS
Now that we have this circuit we implement figure 13.22 found on page
387 of CMOS, by Dr. Baker. This circuit is an edge triggered D-Flip-flop. The
two inverters on the left with the two transition symbols is called the master
latch, while the right side is called the slave latch.
Schematic
Symbol
Layout
DRC
LVS
Simulations
The above simulation shows that Q and Q` both trigger on the
rising edge of the clock input, clk. They trigger on the rising edge to what
the current value of input D is.
Now to implement our circuit in order to detect serial input we
are going to need a AND gate. The size of the AND gate is determined by the
number of bits you want to detect. If we want to detect a 10
bit sequence we will need 10 D Flip-flops and 10bit AND gate.
Schematic
Symbol
Layout
DRC
LVS
Simulation Results
This simulation shows that when in<0:4> (which represents
pins B,C,D,E,F respectively) are high, and then we
have pin A high we output AND high, else we output AND low.
In order to continue we are going to want a buffer for the output
signal. The requirements of the project require us to have a buffer on the
output before we connect it to a pad. We use the equation: 
to calculate the number of stages. We find
that C load is given to us in Lab 8 and Cin is the
modeled capacitance of the inverter. We also like the number 8 for a gain
because it fits well with how inverters work. We find that the N, the number of
stages needed, is just above 3. We need an even number of inverters to make
sure our output is not effected, therefor we will have a total of 4 inverters.
Buffer Schematic
Buffer Symbol
Layout
DRC
LVS
Buffer Simulation Results
The schematic above shows us that the buffer “cleans” up the
signal.
Now we can put everything together, creating the schematic for
detecting a serial input.
Schematic
Symbol
Layout
DRC
LVS
Simulation Schematic
Simulation Results 1
Here we see when given the perfect serial input, 101011, our
output goes high for the light blue line, passes through the buffer and then
goes high for the signal output Detect.
Simulation Results 2
To further prove my design works I am now sending a serial input
1101101011, it will see 1101 and not find anything but then will pick up the
next 6 bits, 101011, and recognize the pattern. It recognizes the signal and
outputs high like it should.