Lab

EE 421L Digital Integrated Circuit Design

Lab 8 – Generating a test chip layout for submission to MOSIS for fabrication

Authored by:

James Garner - Garnerj5@unlv.nevada.edu

Chandon Esplinc2 - Esplin@unlv.nevada.edu

Kyle Deignan - Deignank@unlv.nevada.edu

Fall 2016

Return to: J.Garner EE421 Labs

Return to: K Deignan EE421 Labs

Return to: C Esplin EE421 Labs

Testing Circuits

In order to test the circuits on the chip, please connect the chip to a breadboard and follow the pin table/diagram below. Each Circuit has its own Vdd and shares a global ground, which is pin 20.

The Course Detector Project takes in a 6 bit sequence of either 5V or 0V serially, which represent logic high and logic low respectively. The output, Detect, of this circuit will yield 5V or a logic high for a 6 bit sequence of 101011.

The NAND, NOR, and inverter all operate under logic conditions of 5V as logic high and 0V as logic low. The truth table for these gates can be found easily online. Apply a Value (5V or 0V) to each input, A or B, and the gate will perform the operation.

The PMOS and NMOS gates are standard MOSFETS. In order to test them properly you must use the body pin as well.

The resistive divider is a combination of a 25k resistor and a 10k resistor. To test each resistor individually follow the table below. In order to test the divider itself you must connect an input voltage to pin 21, and ground pin 23 while measuring pin 22.

Pin Table and Picture

Test Circuit Pin	Pin Number	Test Circuit Pin	Pin Number	Test Circuit Pin	Pin Number
c
Course Detector Project		NOR		25k Resistor
Vdd	1	Vdd	11	Plus Terminal	21
In	2	A	12	Minus Terminal	22
Clk	3	B	13
Detect	4	A NOR B	14	10k Resistor
Gnd	20			Plus Terminal	22
		Inverter		Minus Terminal	23
31 Stage Ring Oscillator		Vdd	8
Vdd	6	A	9	25k/10k Divider
Gnd	20	A’	10	25 In	21
Out	5			Divider	22
		PMOS		10 Out	23
NAND		Gate	40
Vdd	15	Source	39	NMOS
A	16	Drain	38	Gate	36
B	17	Vdd	37	Source	35
A NAND B	18			Drain	34
				Gnd	20