Lab 2 - ECE 421L
Garnerj5@unlv.nevada.edu
07-13 September 2016
Return to: J.Garner EE421 Labs
Prelab
Instructions: Prior to coming to lab
make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout (the quiz may
ask a question about this).
In your lab report: 1)
provide narrative of the steps seen above, 2) provide, and discuss, simulation
results different from the above to illustrate your understanding of the ADC
and DAC, 3) explain how you determine the least significant bit (LSB,
the minimum voltage change on the ADC's input to see a change in the
digital code B[9:0]) of the converter. Use
simulations to support your understanding.
Backup your webpages and
design directory.
The first part in this lab
includes downloading the lab2.zip file and adding it to the CMOSeu
directory. Following that we needed to change the cds.lib file, which is
pictured below.
The next steps for the lab
included opening Cadence and going into the lab2 library in the library manager
and navigating to the cell sim_Ideal_ADC_DAC.
This process is pictured below.
The next
picture is the loaded schematic from the step above.
The next
process was launching the ADE, and Loading the State that was already set in
the file.
Then I started
the simulation and got the picture below.
Changing my
reference from 5V to 2V I see that the graph starts clipping at 2V rather than
yielding a 5V result in the picture below. Therefor my signal is bounded by Vref which is 2V.
We can see
that the LSB is equivalent to 
. The initial
problem had a Vref of 5V and n was 10 which is the
number of bits.
Therefor we
see that the LSB in the first problem should be approximately 4.883mV.
Lab Experiment/Post Lab
10-Bit DAC Design:
Using a Resistor Divider Network
Then creating
it as a symbol:
With a N-Well
Design of 10k:
The output
resistance for the given configuration of resistors can be calculated by the Thevenin Equivalent. Using the theory Rout should be
calculated using the following equation:
This will give
us a value of R for any configuration. Therefore:
The Delayed
Load Driving experiment:
In this
experiment I was to compare my hand calculations to the simulated results from
a schematic in which my DAC I created had pins 0 through 8 grounded, while pin
B9 was connected to a time delay signal. Using the Thevenin
theory and simplification of the circuit it can be seen that:
Measuring time
delay can be found using the equation, which is found in the book:
We use this
equation because we are only dealing with 1 resistor-capacitor section, not
through a distributed RC circuit.
As a result,
we find that theoretically our time delay should result in:
The following
picture is the symbol view of my DAC which was created by using the original
DAC symbol and modeling the resistor diagram given in the lab inside of it.
Design
Simulations:
The following
picture is the schematic given in the lab with the Ideal DAC replaced with the
DAC I created.
This next
picture is the simulation results of the DAC with a 20K resistive load:
If my DAC drove
a 10K resistive load, the output voltage would reflect a 50% reduction in the
original Vout. We used a 10K resistive value in the
design so driving a 10K resistive load will just reduce our Vout
to half.
(Voltage
Division)
The next
picture is with a 20k and 1pF load:
The final
simulation is the result of just a 1pF load:
Question:
- In a real circuit the switches the outputs of
the ADC are implemented with transistors (MOSFETs).
- Discuss what happens if the
resistance of the switches isn't small compared to R.
If all the
switches have the same resistance, we will see an addition branch resistance at
every branch. Using the expression above and modifying it to show the new
addition of branch resistance we get:
Changing this
branch resistance will change the voltage drops at each node, in turn changing
the output voltage, time delay and the LSB.