Lab 3 - EE 421L 

First we will design our 10k resistor using the n-well layer. In order to accomplish 

this we must calculate the required length and width of the n-well. We will use sheet

resistance of 800 ohms/square. First we must determine the length to width ratio we

need to obtain this resistance. 

Here we need our length to be 12.5 times bigger than our width. We will choose a width of 4.5 um,

this makes our length 56.25 um. In Cadence I obtained a resistance of 10.2k ohms so I made

some changes to the length to get a resistor closer to 10k ohms.

In the above layout our width is 4.5 um and our length ended up being 54.9 um. This will give me

a resistance of 9.99k ohms.

Now that I have my n-well resistor I can begin connecting them by following the below topology.

In the layout view below we will see the b0 and b1 bits. The b0 bit will have an additional resistor 

in series leading to ground. The b1 bit we see will be copied and placed directly above it until we 

obtain 10 bits.

The below image is our entire 10-bit DAC in the layout view.

The only part of the above layout that is different is the b9 bit. The b9 bit has a Vout pin

connected to it.

All of the pins in the layout are on the metal1 layer.

Now that the 10-bit DAC is layed out I can DRC it.

The layout passed the DRC and now I can extract it and LVS it.

Now that the layout passed the DRC and LVS verifications I can compare my n-well DAC to my ideal DAC.

Before simulating I made sure to add "extracted" before "schematic" in the ADE environment options.

On the left is the Ideal DAC and on the right is the DAC built from n-wells.

		Simulation with no load.
		Simulating delay with 10pF load.
		Simulation with 10k ohm load.
		Simulation with 10pF load.
		Simulation with 10k and 10pF load.

 Here is a link to download the zip file of my Cadence simulations, layouts, and schematics: lab3.zip

I have backed up my labs to my desktop and my OneDrive.

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