Lab 2 - EE 421L 

Prelab Work

First I will read through the entire lab write-up before doing any work.

Next I will download the lab2.zip and upload the extracted files to my cds.lib using the command:

DEFINE lab2 $HOME/CMOSedu/lab2

I will then open up Cadence by typing in the commands:

cd CMOSedu

virtuoso &

In the library manager I will find the lab2 library and open up the schematic view of the 

sim_Ideal_ADC_DAC cell.

The following schematic will open up.

The next step is to simulate the schematic. The simulation results are below.

I changed the background color from black to white. I also changed the lines from dotted to solid and increased

the thickness of the lines for clarity. As we can see, the output signal looks likes a discrete signal due to the 

analog to digital conversion. The ADC will convert an analog signal into a discrete signal and the DAC will convert

the digital signal into an analog signal. The output of this circuit will become more precise with the more bits

we use on the converters. This is because we will decrease the least significant bit, decreasing the minimum voltage to

see change in the digital code.

To determine the least significant bit (LSB) we can use the equation VDD/(2^N) where N is the number of bits

our DAC has. In this lab our VDD is 5V and we have 10 bits. Our LSB is 5/1024 which is equal to 4.88mV.

Lab Procedure

10-Bit DAC Design using 10k Resistors

We will be designing the DAC using the below topology.

By combining the resistors in parallel and series we will end up with an output resistance equal to R. In this design R is 10k.

Below is the schematic that I built in Cadence representing 1-bit of the DAC along with the symbol to represent the schematic.

Since I need a 10-bit DAC I will connect 10 of these symbols together in the configuration seen in figure 30.14.

I will create a symbol for the schematic to make it easier to use in the Ideal_ADC_DAC schematic.

I will now determine the delay of my 10-bit DAC by driving a 10pF load. I will use the equation 0.7RC to determine the 

time delay of my DAC. Since my DAC has an output resistance of 10k we will obtain 0.7(10k)(10p) = 70ns. I will now verify

the results in Cadence. We will connect a pulse source to our B9 pin and connect the rest of the pins to ground. We will add

the 10pF load to the output pin and simulate the schematic.

As we can see from the simulation, when Vout is equal to 1.25V (50% of the 2.5V that the output will go to) we have a time delay of 70ns.

Our prediction is now verified using Cadence.

I will now copy the sim_Ideal_ADC_DAC to a new cell named sim2_Ideal_ADC_DAC and replace the 10-bit DAC in the schematic with

the 10-bit DAC that I created.

When I simulate this schematic I will obtain the results below. I expect the DAC to behave similarly to the ideal DAC I simulated in the prelab.

As we can see in the simulation the 10-bit DAC that I designed works as expected.

I will now simulate the ADC to DAC circuit with various loads attached to the output.

The first load will be a 10k resistor. We can expect the amplitude of the output signal to be half of the input signal

because our DAC has an output resistance of 10k. With a load of 10k we will be halving the output voltage.

From the simulation we can see that my prediction was correct because the amplitude of the output signal is half of the input signal.

I will now simulate the ADC to DAC circuit with a 10pF load. We can expect the output to smoothen out a little bit because of the 

capacitor. We can also expect a delay in the output signal.

As we can see in the simulation, our output signal looks more like an analog signal than a discrete signal and there is a delay of about 75ns.

I will now simulate the ADC to DAC circuit with both a 10k resistor and 10pF load. We can expect the signal to be smoother

as well as the amplitude to be much lower since we are driving a much bigger load.

As we expected, the amplitude of the output signal is much lower than the input signal and the signal is much smoother due to the capacitor. We have a 50ns delay

in the output signal as well.

In a non-ideal ADC to DAC circuit the switches are implemented with MOSFETs. If the resistance of the switches is not small compared to R we will have a

large voltage drop from the ADC to the DAC which will result in a weaker signal going into the DAC.

I will be backing up all of my images and labs into my OneDrive.

I will also be backing up the images and labs onto my desktop.

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