Lab Project – EE 421L

Authored by Chandon Esplin,

EsplinC2@UNLV.Nevada.edu

11/30/2016 

Design, Layout, and Simulation of a Detector

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C.Esplin Detect Design

*Phase I) Design and Simulation of a Detector 11/16/2016

*Phase II) Layout of a Detector 11/30/2016

Design, Layout, and Simulation of a Detector

Experiment(s):

· First half of the project (just the detector schematics, no layout), of your design and an html report detailing operation (including simulations)

· Project - design a circuit that takes a serial input and detects (outputs a high logic signal called detect) the sequence 101011

· The inputs to your circuit are clk and in
Make sure that the output of your design, detect, is buffered before connecting to a pad

Results:

D Flip Flop

Schematic	Symbol
Simulation Schematic	Simulation Results
Layout
DRC	LVS

Transmission Gate

Schematic	Symbol
Layout
DRC	LVS

Inverter

Schematic	Symbol

6-Bit AND

6-Bit Schematic	8-Bit Symbol
Simulation Schematic	Simulation Results
Layout
DRC	LVS

Buffer

N = (1/2)*ln(Cload/Cin) => 1/2 * ln(20pf/(3/2)27fF) ≈ 3 Stages

Schematic	Symbol
Simulation Schematic	Simulation Results
Layout
DRC	LVS

Detector

Schematic	Symbol
Simulation Schematic	Simulation Results
Layout
DRC	LVS

C.Esplin Detect Design

Return to:   C. Esplin EE 421 Labs