EE421 - Lab02 - Esplin

Lab 04 – EE 421L

Authored by Chandon Esplin,

EsplinC2@UNLV.Nevada.edu

09/28/2016

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Pre-Lab Objectives

Learn the necessary skills required for the layout of complex circuits, in particular MOSFET Transistors. Reinforce the habit of backing up and storing previous versions of both completed work and the technical libraries used. Further develop and expand upon foundational skills with Cadence software.

Pre-Lab Tasks

1. Back-up all of your work from the lab and the course.

2. Read through this lab before starting it.

3. Go through Tutorial 2 seen here.

4. In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Experiment(s):

Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):

A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.

Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).