Lab 02 – EE 421L
EsplinC2@UNLV.Nevada.edu
Pre-Lab Objectives
Gain and demonstrate intimate knowledge of both Analog-to-Digital & Digital-to-Analog Converters [ADC & DAC], in preparation of, the design of a 10-bit DAC. Reinforce the habit of backing up and storing previous versions of both completed work and the technical libraries used. Further develop and expand upon foundational skills with Cadence software.
Pre-Lab Tasks
1. Provide narrative of Pre-Lab
2. Provide differing simulations (from example) and discuss results to demonstrate knowledge of ADC & DAC
3. Explain method of determining the Least Significant Bit (LSB, the minimum voltage change on the ADC’s input to see a change in the digital code B[9:0] of the converter. Provide simulations in support of explanation.
Pre-Lab Data
(1) Narrative
Creating back-ups of previously completed work prior to reading through laboratory
Downloading the entire user created CMOSedu directory, zipping, and dating.
*Note: This process proved to be time consuming and excessive for back-up purposes. Next back-up will consist only of user altered files and directories.
Downloading, uploading, and unzipping lab2.zip to cds.lib in design directory
The previously created directory CMOSedu is the target destination to upload lab2.zip. Once unzipped, the cds.lib file will need the statement DEFINE lab2 $HOME/CMOSedu/lab2 added before Cadence will recognize the newly added converters.
Load schematic of sim_Ideal_ADC_DAC & run simulation
The above simulation shows the input voltage Vin, an analog signal, deconstructed into digital components and reconstructed back into an analog output voltage Vout.
(2) Provide & Discuss Simulations
Altering the amplitude of Vin to a higher voltage than Vref
Vref limits the bounds of Vout, as seen above when the amplitude of 3 volts exceeds the 0-5 limit, clipping occurs.
Increasing Vref to 10 volts with a relative increase to Vin
There is a limit to where Vref can be increased without diminished returns.
Vref set equal to Vin offset (2V)
Further demonstration of the constraint Vref has over the output voltage.
(3) Explain: Determination of Least Significant Bit
As found in CMOS Circuit
Design, Layout, and Simulation 3rd edition
The least significant bit is given by: Using the initial example values of:
n=10 & Vref
=5 V
The Least Significant Bit:
4.883mV
Simulation of Vin set just above LSB viewed below
As seen in this simulation, the resolution of the reconstructed signal is down to one bit.
Lab: Design of a 10-bit digital-to-analog converter (DAC)
Experiment(s):
· Design - 10-Bit DAC with 10kΩ n-well Resistors
· Determine Output Resistance
· Time Delay - Driving a Load
· Symbol Creation
· Simulations of Various Load Types
Results:
· Design - 10-Bit DAC with 10kΩ n-well Resistors
10-Bit DAC Schematic
Output Resistance Determination
Parallel to Series
Combining 2R in parallel with 2R produces R in series with R. This parallel/series reduction and recombination continues, resulting in a total resistance of R.
Delay, Driving a Load
Time Delay Circuit
Symbol Creation
Created DAC Symbol
Simulations of Various Load Types
Resistive
Capacitive
Resistive-Capacitive
Discussion:
In
reality, the switches used within the converters are implemented with
transistors. Discuss the outcome if the resistance of the switched is not small
relative to R.
If left unaccounted for, the addition of a new series resistance will alter the parallel/series decomposition and reconstruction. This chain reaction will cause the previously even distribution of bits to be altered. The end result will be larger sources of errors and failure to obtain the number (1024) bits as designed.
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