LAB 8 - EE 421L Digital Integrated Circuit Design

Authored by

Charlie Torres-Garcia     torresga@unlv.nevada.edu

Ulises Diaz                      diazu@unlv.nevada.edu

Antanasia Jones              jonesa20@unlv.nevada.edu

12/06/2016

Project: - Generate a test chip layout for submission to MOSIS for fabrication.

Each test circuit should have its own power and ground should be shared between the circuits. 

"Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable"

  
The chip will include the following test structures:

• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u
• 25k resistor laid out below and a 10k resistor to implement a voltage divider
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)  
• A Detector circuit (sequence 101011)
  

     

FULL CHIP LAYOUT:
 Schematic:                             Layout:               
  

Pin LIST:

31-Stage Ring Oscillator:

      Schematic:                                    

            NMOS:                     PMOS:                  

Schematics:                                              

                                                            

       

                NAND:                               NOR:                  

Schematics:   

               
                

  

  

Detector:

   Schematic:  

FULL CHIP:
We finally DRC and LVS the chip to make sure that everything works properly for submission to MOSIS fabrication. 
DRC:                             LVS:

Chip2_f16.zip

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