LAB 8 - EE 421L Digital Integrated Circuit Design


Authored by

Charlie Torres-Garcia     torresga@unlv.nevada.edu

Ulises Diaz                      diazu@unlv.nevada.edu

Antanasia Jones              jonesa20@unlv.nevada.edu



12/06/2016



Project: - Generate a test chip layout for submission to MOSIS for fabrication.


Each test circuit should have its own power and ground should be shared between the circuits. 

"Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable"

  
The chip will include the following test structures:


The padframe follows the bonding diagram below.     Pins < 1 > --> Pin < 40 >             size: 1440um by 1440 um
     


FULL CHIP LAYOUT:
 Schematic:                             Layout:               
  
Pin LIST:


REMEMBER     pin < 20 >     IS GROUND FOR ALL TEST CIRCUITS & VDD = 5V !!!!!!!!

31-Stage Ring Oscillator:
      Schematic:                                    

            NMOS:                     PMOS:                  
Schematics:                                              
                                                            
       
                NAND:                               NOR:                  
Schematics:   
               
                
INVETER:                               XOR:                  
Schematics:   
                                                                  
       

Voltage Divider (25k & 10K resistors)
       Schematic:   
  

FULL-Adder:
     Schematic:   
  

Detector:
   Schematic:  



FULL CHIP:
We finally DRC and LVS the chip to make sure that everything works properly for submission to MOSIS fabrication. 
DRC:                             LVS:



Chip2_f16.zip





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