Lab 6 - EE 421L 

Authored by Ulises Diaz Jr.

Email: diazu@unlv.nevada.edu

Date: 10/26/16

  

Pre-lab:
 Lab:

The purpose of this lab was to gain more practice with Cadence, and be able to create a schematic, symbol, and layout for two different logic gates by going through Tutorial 4. Basically, an NAND gate is a digital logic device that produces an output signal until there are signals on all of its inputs. The next logic gate for this lab is the XOR (Exclusive OR) gate. For the XOR gate, a HIGH output results if and only if one of the input signals is HIGH. Additionally, if both of the inputs to the XOR gate are HIGH or LOW, then the output will be LOW. For this lab, a 2-input NAND gate and XOR gate will be implemented to create a full-adder logic circuit.

Part 1 (NAND Gate):

First, I went over Tutorial 4 from the prelab to design the schematic, symbol, and layout for the NAND gate digital logic device. The NMOS and PMOS widths and lengths used for this gate were both 6u/0.6u. The figures below show the schematic, symbol, and layout for the NAND gate:
NAND Gate Schematic                                                                              NAND Gate Symbol


NAND Gate Layout, DRC, and LVS:


Part 2 (XOR Gate):

Next, I created the schematic, symbol, and layout for the XOR gate. Below are the figures:

XOR Gate Schematic                                                                                         XOR Gate Symbol


XOR Layout, DRC, and LVS:

Part 3(Simulating the NAND and XOR Gates):

After creating the schematics for the NAND and XOR gates, the next step of the lab was to make sure the gates are functioning properly. The gates were tested under the following inputs: AB = 00, 01, 10, 11. Below are the truth tables for each logic device:


The following figures show the schematic used to simulate the logic gates and the simulation results:

Notice in the output for the XOR gate, there is somewhat of a glitch. The reason for the glitch is that input A is on the rising edge while input B is on the falling edge. Therefore, the output of the XOR gate is false briefly, then goes to HIGH until both inputs reach the same value. For this simulation, at approximately 210 ns the output is HIGH which is the correct value after the glitch in the simulation. 

Part 5( Full-Adder Schematic, Symbol, Layout, and Simulation):

Finally, the last part of this lab is to create the schematic, symbol, layout, and simulation for the full-adder using NAND and XOR Gates. Below are the figures for the full-adder logic circuit:

full-adder schematic                                                                                                      full-adder symbol


full-adder layout, DRC, and LVS:


full-adder simulation results:




As with the previous simulation of all the logic gates, the full-adder experiences a similar glitch. The reason behind the glitch is the same as what happened with the XOR gate, one input is on the rising edge while another input is on the falling edge at the same time. This causes a brief false output until both inputs become the same value to output correctly. For this simulation, at approximately 310 ns the output is HIGH which is the correct output value for the full-adder after the glitch.

This concludes my lab report. Below you will find the zip file for all the cells used in this lab.

lab6_ud_f16.zip
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