Lab

Lab 4 - EE 421L

Authored by Ulises Diaz Jr.

Date: 9/28/16

Pre-lab:

I backed up all of my work from lab 3 and the course.
I finished going through Tutorial 2.
As stated before, all the NMOS devices in this lab have their body connected to ground, and all the PMOS devices should have their body connected to VDD (5V).

Lab:

Part 1:

The purpose of this lab was to gain more practice with Cadence, and be able to create a schematic, symbol, and layout for both the NMOS and PMOS devices. After creating the schematics, I then created a symbol for both the NMOS and PMOS, and finally simulated my schematic using the symbol. Note: The lengths of the NMOS and PMOS devices for the design were 6u/600n and 12u/600n, respectively.

1.) I first began this lab by creating the schematic for the NMOS first. From Tutorial 2, the NMOS length was set to 6u/600n. The figure below shows my schematic for the NMOS:

*Note: Tutorial 2 began the the NMOS schematic as a 3-terminal device, however Cadence defines NMOS and PMOS as 4-terminal devices (includeing the body or substrate connections). Therefore, I began my NMOS schematic as a 4-terminal device.

2.) Next, from the NMOS schematic I created a symbol for the NMOS to be able to simulate it. The purpose of creating the symbol was to make simulations from extracted layouts much easier to perform. The image below shows my NMOS symbol:

3.) The next step is to create a simple circuit to simulate ID vs VGS for the NMOS device. The following figure shows the circuit from the Tutorial that is used:

4.) The simulation of the NMOS involved a different, but simple process to simulate ID vs. VGS. Basically, it was a linear sweep of VGS from 0 to 5V in 1V steps, and simulating ID throughout the sweep voltages. From the circuit, source V1 is set to 0 for the linear sweep, and VGS is set as the variable for the parametric analysis to plot the I-V curves of the NMOS. The results of the sweep and parametric analysis are shown below:

5.) After running the parametric analysis sweep from 0 to 5V, the next simulation was simulating the same NMOS device but with VDS = 100mV. Therefore, I would only need to sweep VGS from 0 to 2V, in 100 mV steps. A parametric analysis wasn't required for this simulation.

6.) After creating the NMOS schematic, symbol, and circuit for simulation, the next step in the tutorial was doing the same exact thing, but for a PMOS device instead. Below is my PMOS schematic:

PMOS Symbol:

*Note: Since this is a PMOS device, the body (substrate) must be connected to VDD (5V).

PMOS Circuit for simulation:

Simulation of the parametric analysis sweep (sweep VSG from 0 to 5V in 1V steps and sweep VSD from 0 to 5V in 1mV steps):

Simulation of the dc sweep (sweep VSG from 0 to 2V in 1 mV steps while VSD = 100mV):

Part 2:

The next part of this lab required to layout both NMOS and PMOS devices. After laying out the devices, I connected the 4 terminals of each device to pads. Lastly, I then made a schematic of the probe pads to LVS the netlist from the layout and the schematic. I separated the layouts and the schematics in two different tables:

Table 1

NMOS Layout DRC	NMOS with probe connection DRC
PMOS Layout DRC	PMOS Layout With Probe Connections DRC

Table 2

NMOS Schematic with Probe Pad Connectors LVS	PMOS Schematic With Probe Pad Connectors LVS

This is the end of my lab report.

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