Lab 3 - EE 421L 

Authored by Ulises Diaz Jr.

Email: diazu@unlv.nevada.edu

Date: 9/20/16

  

Pre-lab:
 Lab:

Part 1:

1.) Before laying out the 10k n-well resistor, we needed to figure out how to calculate the dimensions of the n-well in order to acquire the desired resistance of 10k. Based on the process information from MOSIS, the sheet resistance of the n-well is 800 ohms/square and the minimum width required is 12 lambda, or about 3.5 microns. My hand calculation below shows how to get the 10k value for the n-well resistor:



Choosing 4.5 microns for W and 56.25 microns for L would give us 10k, However if we do L/0.15 or 56.25 microns/0.15 that's equal to a whole number so when we DRC the layout we would not get errors that cause pain.

2.) After laying out my 10k n-well resistor and extracting it, I got a resistance of about 10.21K as shown in the image below:



Part 2:

1.) After I successfully extracted my 10k n-well resistor, the next step of the lab was to layout the following DAC Resistor ladder:



2.) I began the layout of the DAC Resistor ladder by connecting the b0 pin first. Therefore, after I make the connections I can then copy the b0 connection and rename all the new copies all the way up to the b9 pin. My layout and connection is shown below:



The next image shows my full DAC Resistor Ladder layout:



3.) The next step after finishing the layout is running the DRC and LVS. After a lot of work, my layout finally matched the DAC schematic, and the netlists matched. The results are shown below:

DRC


LVS

LVS Netlist


3.) After successfully laying out my DAC, the next step is to simulate the ADC to DAC using my layout and plotting the results.

Here is my symbol:

ADC_DAC:


The following table will compare my simulation results from using my old symbol to using my extracted layout symbol under the following loads:


No Load (Old Symbol)



 No Load (Extracted Layout Symbol)
10 K Resistor Load (Old Symbol)
 10 K Resistor Load (Extracted Layout Symbol)
10 pF Capactor Load (Old Symbol)
 10 pF Capacitor Load (Extracted Layout Symbol)
RC Load (Old Symbol)

 RC Load (Extracted Layout Symbol)
All pins ground but b9 with a pulse source and 10 pF load (Old Symbol)


 All pins grounded but b9 with a pulse source and 10 pF load (Extracted Layout Symbol)



This is the end of my lab report.

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