Lab 2 - EE 421L 

Authored by Ulises Diaz Jr.

Email: diazu@unlv.nevada.edu

Date: 9/12/16

After I downloaded the lab2 zipfile, I launched Cadence to open up the following schematic:

This Schematic is an ideal ADC to DAC. The output of the ADC to DAC is shown in the figure below: 

ADC to DAC Operation: Based on the previous simulations, one can see the purpose of an Analog-to-Digital converter is to take the output of an analog signal (sinusoid in this case), and to quantize the signal as accurately as possible to convert it into a digital signal. Furthermore, a Digital-to-Analog converter does the reverse operation of taking the quantized digital signal from the ADC, and convert it back to analog. To prevent aliasing, a filter is typically used to remove undesired frequencies before converting the analog signal to digital. If the input voltage is changed to anything above 5 V, the output signal clips:

Additionally, in the lab a 10-bit ADC to DAC is used. Therefore, the number of possible input combinations are: 2^10 or 1024 inputs.

How to determine the LSB (Least Significant Bit): The LSB means the right most bit in the digital input determines the smallest change in output voltage. The least significant bit is determined by using the equation: Vref/2^n. In this case, the least significant bit is calculated to be: 5 V/2^10 or 4.88 mV. The following simulation shows how the output changes by one bit when Vin is 4.88 mV:


Lab:

1.) In this part of the lab, 10k n-well resistors will be used to implement a 10-bit DAC based on this topology from the CMOS book:

However, since the figure shows the topology for a 5-bit DAC, the only difference to make a 10-bit DAC was to add 5 more serial resistors. The next figure shows my implementation of the 10-bit DAC using 10k resistors:



2.) The next step was to create a symbol based on the last figure of the serial resistors. Here is my symbol I created:



To calculate the output resistance of the DAC, one simply takes the 2R resistor in parallel with 2R starting at b0. This simplifies the resistance to R. You repeat this process all the way up to b9. The following shows my hand calculation of the output resistance:

Next, I simulated my 10-bit DAC symbol with a 10 pF load to calculate my time delay. The time delay is given by td = 0.7RC. Therefore, td = 0.7*10k*10p which is equal to about 70 ns time delay. The next figures support this calculation:



3.) The last part of this lab was to finally connect my 10-bit DAC symbol to the ADC, and simulate a non-ideal 10-bit ADC to DAC under the following loads:

No Load: Since this is a non-ideal ADC to DAC, there may be some inconsistencies in the ouput as shown in the simulation to the right.
10k Resistor Load: The amplitude of the output voltage signal is decreased because the 10k resistor load acted as a voltage divider for the output. The simulation demonstrates this to the right.
10 pF Capacitor Load: Adding the 10pF capacitor to the output of the circuit adds delay and phase shift to the output as shown in the simulation.
10K Resistor and 10 pF Capacitor (RC Load): The output signal experiences an RC effect giving it both the delay phase shift and reduction in the amplitude of the signal.