Lab 7 - EE 421L
deignank@unlv.nevada.edu
Pre-lab work:
Back-up all of your work from the lab and the
course.
As shown below,
I am using google drive to back up all my work from the lab:
Go through Tutorial 5:
Tutorial 5 explained how to create a schematic
and layout of a 32 stage ring oscillator. It also went over simulations.
Screenshots from the tutorial are shown below:
Schematic:
Layout:
Lab:
The first part of the lab consisted of creating a concise
schematic for a 4-bit inverter. My symbol for the schematic and simulation
schematic are shown below:
The simulation results from the above circuit are shown below:
These are the expected results from a 4-bit inverter. As shown
above the value of the capacitor will affect the response time of the inverter.
Out<3> was the fastest with the lowest delay, correlating to the lowest
capacitance.
The lab then asked to create schematics and symbols for 8-bit
NAND, NOR, AND, inverter, and OR gates.
NAND:
NOR:
AND:
OR:
Inverter:
I included all of these gates into and simulation schematic and
with every combination, shown as net1 and net2 in the waveforms. The outputs
from the simulation matched what we would expect from each of the gates. The
results and schematic are shown below:
AND:
The outputs are only high when both inputs are high.
NAND:
The outputs are low at all combinations except when the inputs are
1 1.
OR:
The outputs are always high except for 0 0.
NOR:
The outputs are always low except for 0 0.
The next part of the lab asked to simulate and understand the
2-to-1 DEMUX/MUX. The schematic and simulation are shown below:
The schematic outputs either A or B depending on what logic the
selector bit is at. The results are consistent with this explanation. The first
cycle shows an output of A (5v) and the second an output of B (0V).
The lab then asked to create an 8 bit wide 2-to-1 DEMUX/MUX. This
was accomplished using the same method as tutorial 5, with buses. An inverter
was included so only a selector bit is needed. Below is the schematic:
I then created a symbol for the schematic for simulations. Below
is the symbol and simulation results, which are the results we would expect.
For the above simulation the same selector signal was used for
all the bits. The simulation is what we would expect for a multiplexer.
The last part of the lab was to create a full-adder schematic, and
extend it to an 8-bit wide full adder, similar to the components above.
Single bit full-adder schematic and symbol:
A layout of the single bit full adder is shown below which LVSed and DRCed.
As shown above the netlists matched.
I created a schematic from the above symbol for an 8-bit wide
adder by changing the way it is instantiated and adding buses to the inputs and
outputs. Pins Cn and cout will be the input and
output of the cascaded full-adders as well as An<7:0>,
Bn<7:0> and the sum outputs Sn<7:0>. The
schematic, symbol, and simulation are all shown below:
The final layout passing DRC and LVS is shown below:
The netlists matched as shown above.
I used google drive to backup all my
files:
