Lab 6 - EE 421L
deignank@unlv.nevada.edu
10/25/2016
Design, layout, and simulation of a CMOS NAND gate, XOR gate, and
Full-Adder
Pre-Lab
The pre-lab consisted of creating a nand
gate using transistors and laying it out.
Below are some screenshots of the tutorial:
Lab:
Draft the
schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig.
12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
Create layout
and symbol views for these gates showing that the cells DRC and LVS without
errors
ensure that
your symbol views are the commonly used symbols (not boxes!) for these gates
with your initials in the middle of the symbol
ensure all
layouts in this lab use standard cell frames that snap together end-to-end for
routing vdd! and gnd!
use a standard
cell height taller than you need for these gates so that it can be used for
more complicated layouts in the future
ensure gate
inputs, outputs, vdd!, and gnd! are all routed on
metal1
Use cell names that include your initials and the
current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)
nand Schematic: nand Layout:
nand Symbol:
nand DRC:
nand LVS:
xor Schematic: xor layout:
xor symbol:
xor DRC:
xor LVS:
Using Spectre simulate the logical operation of the gates for all
4 possible inputs (00, 01, 10, and 11)
comment on how
timing of the input pulses can cause glitches in the output of a gate
Simulation Schematic:
Waveform:
The outputs are what we would expect to see. The fast switching in
the inputs causes the lines seen in between values, such as the bottom green line
at 200ns.
Using these gates, draft the schematic of the full
adder seen below
Create a symbol for this full-adder (example)
Simulate, using Spectre,
the operation of the full-adder using this symbol
Layout the full-adder by placing the 5 gates
end-to-end so that vdd! and gnd!
are routed
full-adder inputs and outputs can be on metal2 but
not metal3
DRC and LVS your full adder design
Below is the
schematic for my full adder:
The layout is
shown below: 
DRC:
LVS:
Simulation Schematic:
Waveform:
The results are consistent with the truth table provided in the
lab.
I am used google drive to back up all the work that was completed
in this lab.