Lab 5 - EE 421L
deignank@unlv.nevada.edu
I use google
drive to back up all the material from the lab. My drive is shown below:
The pre-lab
asked us to go through tutorial 3. This tutorial consisted of creating a CMOS
inverter schematic and layout, and running a few simulations with it. Below are
some screenshots from the tutorial:
Lab:
The first part
of the lab consisted of creating two different inverters. The first was 12u/6u
and the second 48u/24u. Because they are multiples of each other, the second
schematic was easily made from the first one by setting the multiplier value to
4. The two schematics are shown below:
The lab also
asked to create a symbol and layout view for each of the schematics above and
DRC and LVS the designs. Screenshots of each of these are shown below:
12u/6u:
48u/24u
The lab also
asked to simulate each of the inverters driving a 100fF, 1pF, 10pF, and 100pF
load using UltraSim. This was achieved by setting the
capacitor value to a variable and using the parametric analysis feature to
sweep in decade steps.
12u/6u
100fF
1pF
10pF
100pF
Examining the
waveforms above show that as the load increases in capacitance the output
changes less rapidly. As seen in the last simulation, the output sees a
constant 5V because the capacitor supplies enough charge to hold the node
constant through the whole cycle due to the large time constant.
48u/24u
100fF
1pF
10pF
100pF
Once again, it
is seen that as the capacitance of the load goes up, the output changes less
rapidly due to a larger RC time constant. Because the R in the RC time constant
is specific to the dimensions of the MOSFET, we see slightly different results
in the above waveforms then for the 12u/6u inverter.
Using spectre as the simulator led to similar results. Waveforms
showing the output for each capacitor value are shown below for both inverters:
12u/6u
48u/24u
My google
drive backups are shown below:
My working
directly is zipped and linked here.
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