Lab

Lab 4 - EE 421L

Kyle Deignan

deignank@unlv.nevada.edu

9/28/2016

Pre-Lab:

I am using google drive for my backups as seen below:

Tutorial 2 consisted of creating a schematic using an nmos and simulating the IV characteristics. It also included laying out an nmos, and using the layout for the simulation. At the end, it repeated everything above with a pmos. Below are some screenshots from going through tutorial 2.

NMOS:

Schematic: Simulation: Layout:

PMOS:

Schematic: Simulation: Layout:

LAB:

A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio:

To simulate ID v. VDS while varying VGS we first set the voltage source for the gate to “VGS.” We then set vdc to 0. This is arbitrary as we well sweep it during the simulation.

After launching the ADE we go to Variables-Edit and set VGS as a variable. We then choose the analysis as DC and select “Component Parameter” under “Sweep Variable.” Enter “/V1” as the component name and choose the range as 0 to 5 in 1m intervals. After completing the above we go to tools-parametric analysis. Here we set VGS to sweep from 0 to 5. Selecting start from that window gives us the following simulation:

A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio:

For this part we follow similar steps as above, except we keep VDS at a fixed value of 100mV. The schematic is shown below with VDS as 100mV and VGS as 0V:

For the simulation we remove the variable VGS and use a DC analysis to sweep VGS from 0 to 2V in 1mV intervals. The simulation is shown below:

A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio:

This part of the lab is similar to the first part except we use a pmos. It’s important to connect the body of the pmos to vdd as shown below in the schematic:

Since two voltage sources are varying, we follow the same procedures as the first part of the lab. VSD is swept in the DC analysis and VSG is swept as a variable using the parametric analysis. The simulation is shown below:

A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio:

For this part of the lab we use the same schematic as shown above, except we change VSD to a fixed 100mV and sweep VSG using the DC analysis from 0 to 2V in 1mV increments. The schematic is shown below: