Lab 2 - EE 421L
Pre-lab:
The pre-lab
first asked to download and extract a zip file into my home directory on the
cadence server. After this it asked to define the library in the cds.lib file.
The pre-lab
then asked to open the “sim_Ideal_ADC_DAC” schematic
and run the included simulation. The simulation results and schematic are shown
below:
Schematic:
Simulation:
The circuit
shown takes a sine wave input voltage and converts it to a digital signal with
an ADC. The digital signal is then fed into a DAC and converted back to AC. The
output is shown in brown in the above simulation. The waveform clearly shows
the loss of resolution in the signal due to the ADC quantizing the input.
The least
significant bit is determined by dividing the max output by the total number of
combinations. In this case, we are using a 10 bit DAC so the total number of
combinations is 210 = 1024. The max signal value in this case is 2.5
V. Using these we get 2.5/1024 = 2.4 mV
Lab:
The first part
of the lab asked to design a 10-bit DAC using 10k n-well resistors. We were
provided with the following schematic to use as a reference:
Output Resistance:
The total
equivalent resistance of the DAC can be easily found by combining the resistors
in parallel. The bottom 2R and next 2R are in parallel which is equivalent to
R. This is now in series with the next R which add to 2R and is parallel to the
next 2R. Repeating this process all the way up the circuit results in an
equivalent resistance of R.
My schematic
for the DAC is below:
I created a
symbol of this circuit by going to create→ cell view → From cell
view, which is shown below:
I then
repeated the initial simulation but using the symbol I created in place of the
ideal DAC. The schematic and simulation are shown below.
As shown
above, the simulation matches the simulation using the ideal DAC.
Delay, driving
a load:
When driving a
10K load, the circuit essentially becomes a voltage divider with the load and
the equivalent resistance of the DAC. The simulation below shows the results of
adding a 10K load.
The 10K load
cuts the peak output in half, due to voltage division.
Vout = Vin (10k/20K) = 1/2Vin
The delay of
the circuit when adding a 10pF load can be found with .7RC which calculations
as (.7)*(10k)*(10p) = 70ns. The simulation and
schematic are shown below:
If we were to
simulate using an RC load, we would get a lower peak output voltage that would
also be shifted by some delay equivalent to (.7)(Req)(C).
If
non-negligible resistances are found in the switches in the DAC then this will
factor into the voltage drop at each node, resulting in a higher voltage drop
across the DAC than intended. This will distort the digital.
I used google drive to back up my files as shown below.
