Lab 7 - ECE 421L 

Authored by Dominique Anguiano,

Email: anguian3@unlv.nevada.edu

November 10, 2016

  

Pre Lab

  

The Pre Lab for this week introducd us to using arrays and buses in making schematics.  Using these tools helps make schematics cleaner and easier to read as a result.  This was the main focus of the prelab and this was used extensively throughout the lab for this week.

Lab Report 

 

1) 4-bit inverter

  

We begin this lab by creating a four bit inverter.  The inverter uses a 6u/0.6u NMOS and PMOS.  The process for making this inverter was covered in the lab and is very simple.  All it requires is that a bus be made as well as an array and some appropriate labels be used.  The four-bit inverter can be seen below.

Inverter_4_bit_schematic.PNG

  

The Symbol of the device was used in the simulation which can be seen below.

 

inverter_four_bit_schematic.PNG  inverter_four_bit_sim.PNG

  

 The simulation of the device had us attach loads of varying capacitances to each of the outputs of the inverter in order to observe the effects of a higher output capacitance.

As we can see from the simulation, placing higher capacitive loads on the outputs of this gate results in a slower rise time that is a result of the capacitors needing to charge.  The discharge time is also increased.  This simulation shows how timing may be affected if a higher capacitive load is added to the output of a gate.  The increased time to charge would require that a signal be supplied for a longer period of time before it can be read as an output "high" or "low".

 

 

 2) Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter and OR gates

   

The same process was used to create these gates as for the 4-bit inverter.  The Schematic and Symbols of the devices may be seen below

 

    NAND

 
NAND_8_bit_schematic.PNG NAND_8_bit_symbol.PNG


 
      NOR
 
 NOR_8_bit_schematic.PNG  NOR_8_bit_symbol.PNG

    

   

    AND
  

 and_8_bit_schematic.PNG  and_8_bit_symbol.PNG

    

   

    Inverter
  

 Inverter_8_bit_schematic.PNG  Inverter_8_bit_symbol.PNG

    

   

    OR
  

 OR_8_bit_schematic.PNG  OR_8_bit_symbol.PNG

    Simulation of the gates

 The simulation of the gates was all done in one schematic which can be seen below.  In order to make the simulations easier to read, only two gate outputs from each array were shown. Also, the outputs from each array are colored similarly so it becomes easier to see which output is from each set of gates.   The outputs on the schematic from top to bottom are: A, B, Inverter, AND, NAND, OR, NOR.

Gates_Schematic.PNG   Gates_sim.PNG

 

 

 

 3) DEMUX/MUX

The schematic and symbol for the mux can be seen below.  In order to simplify the symbol slightly, the inverter was included in the symbol so that a user would only have to supply one signal (s) to select the output of the device.

  

 Mux_Schematic.PNG  Mux_Symbol.PNG

Operation of the Mux/Demux

A mux is supplied two inputs at terminals A and B which can be seen in the above schematic.  These inputs are connected to the drain and source of an NMOS and PMOS device.  There is a set of these devices for each input into the mux.  The gates of these devices are connected to a selection signal.  In our schematic, this signal is supplied by terminal S.  When a signal is supplied to S, it will turn off one set of NMOS and PMOS devices and turn on the other.  This allows one input (A or B) to flow through the MOSFETs and be output at Z.  In a Demux, A and B are the outputs of the device and Z is the input.  S determines which output Z will flow to in the same way it does for the mux.  

 

Simulation of the MUX

The simulation of the MUX device can be seen below.   

Mux_2_to_1_schematic.PNG  Mux_2_to_1_sim.PNG


 As we can see, the device operates as expected and switches outputs whenever S is changed.

 
 

Simulation of the DEMUX

The simulation of the DEMUX device can be seen below.   

 

DeMux_2_to_1_schematic.PNG  Demux_2_to_1_sim.PNG

  

As we can see, the device routes the input to either A or B depending on the value of S.

 4) 8-bit DEMUX/MUX

 The 8-bit schematic of the MUX/DEMUX was created using arrays and busses.  The device can be seen below.

   

Mux_8_bit_schematic.PNG  Mux_8_bit_symbol.PNG

    

   

The simulation of the device for a MUX configuration can be seen below.

  

  Mux_8_bit_sim_schematic.PNG  Mux_8_bit_sim.PNG

The simulation of the device for a DEMUX configuration can be seen below.  

 Demux_8_bit_sim_schematic.PNG  Demux_8_bit_sim.PNG

 

 

 

 

 5) Full Adder

The final part of the lab required that we layout the full adder seen in figure 12.20.

 

 We begin by creating the schematic and symbol

 

Adder_Schematic.PNG  Adder_Symbol.PNG

 

The Layout view of this adder can be seen below

 

 Adder_Layout.PNG



The Extracted view of the adder can be seen below

Adder_Extracted.PNG

 6) 8-Bit Full Adder

Now that the Full Adder was created, we now use it to create an 8-bit adder.

The Schematic and Symbol of the 8-bit adder can be seen below.

 

Adder_8_bit_schematic.PNG  Adder_8_bit_symbol.PNG



We then simulate the operation of the 8-bit adder.
In the schematic that follows, the values of A: 10001001, B: 10001010  and C: 1 are being added together, this should result in a value of 00010100 at the output.
 
Adder_8_bit_sim_schematic.PNG  Adder_8_bit_sim.PNG

As we can see from the simulation, the device works as it should.

The Layout and DRC results of the device can be seen below.

 

Adder_8_bit_DRC.PNG

And here is the extracted view

Adder_8_bit_Extracted.PNG
 
 

And of course, we can't forget the LVS results

 
Adder_8_bit_LVS.PNG
  

This Concludes the epic adventure known as Lab 7.

 

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