Lab

Lab 2 - ECE 421L

Authored by Dominique Anguiano,

Email: anguian3@unlv.nevada.edu

9/6/2016

Pre Lab

Part 1)

For this lab, we begin by ensuring that we have a backup of all of the work from the lab and the course in order to help prevent the loss of any valuable data. After this was completed, I then read through the entire lab 2 write-up in order to have a basic understanding of what was going to be occuring in this week's lab.

Once I was finished reading through the lab, I then began by downloading the lab2.zip file to the desktop.

This file was then uploaded to the design directory that Cadence resides in and was then unzipped.

The original zip file and the unzipped folder can be seen in the image above. These files were uploaded to my CMOSedu folder.

Once I had done this, I then needed to modify the cds.lib file in order to be able to see the directory in the library manager in Cadence. This was done by adding the highlighted line seen in the image below.

Now that all of the setup was done, it was then time to open up the schematic of the 10-bit ADC.

With the schematic open, we ran the simulation and modified the graph in order to make it a bit more readable.

In the image seen above, the background of the simulation graph was modified as well as a few of the settings on the lines. These settings were accessed by right clicking the background and right-clicking the label of each line.

The settings that were modified,were the width, style, and color. The width affects the thickness of the line. For my simulations, this thickness was set to medium. Style affects whether you want a solid or dotted line or any other style from the few that are offered.

Once this was all done with the default simulation, I then moved onto to part 2 of this prelab which required me to provide simulation results different from the lab.

Part 2)

In the simulation that is shown below, the ADC receives an input signal that is shown by the red line below. This input signal is then converted by the ADC into a binary number that is depicted by the purple line also seen below. This binary number represents the level of the signal when compared to VDD. As long as the level of the signal is less than VDD and above 0, the binary number that is created will be an accurate representation of the input signal. A DAC converts the binary numbers generated by the ADC back into a signal. This signal will have nearly the same values as the original as long as it was not greater than VDD. If it was greater than VDD at some points, those points will be shown as VDD or Zero, and data from the original signal will have been loss. All other points will be close approximations of the original signal due to how the signals must have been interpolated in order to be represented as binary values.

Part 3)

The least significant bit (LSB) is determined by both VDD and the number of bits used for the ADC. It is a ratio between these two values and is given by the formula

If the read voltage falls under the value given by this formula, the value output by the ADC will be 0. This can be seen below.

If the value for in the input signal goes above the value for the LSB, then the value output by the ADC will change.

Lab Report

Design of a 10-bit DAC using 10k resistors

The design of a 10-bit DAC can be done by purely having a 2R resistor in parallel with an R resistor as shown below.

This arrangement of resistors is then repeated multiple times until the number of inputs matches the amount of bits desired for the DAC. In this lab, we require a 10-bit DAC so we will repeat this arrangement by connecting the "Out" pin to the 'A' pin for each arrangement. The completed 10-bit DAC schematic is shown below.

Now that we have the 10-bit DAC schematic, we must turn it into a symbol. This is done by selecting the option shown below and following all of the window prompts.

Once this is completed, the symbol should open up in a new window and look like this. Note, since this design will not use VDD, Verfp, or Vrefm those may be deleted.

Simulations

In order to verify that my 10-bit DAC functions correctly, I replaced the DAC in the ideal simulation with the DAC I created in order to see the waveform it produces.

As we can see, the DAC created in the lab produces a fairly accurate result for the majority of the waveform with an acceptable accuracy.

Now, we can begin testing of this DAC with a load that consists of either an R, C or R/C.

With an R load of 10k ohms, Vout is reduced by about 50%. This is because the load R has an equivalent resistance to the DAC's output resistance. The calculation of this output resistance will be seen later in the report.

Adding a 1pF Capacitor as part of the load causes two things to occur to the output of the DAC. The first is that the staircase effect is removed and we end up with a smoother curve. The second is that a small delay of around 20ns is introduced to the output.

Adding both a 10pF Capacitor and 10k Ohm Resistor causes there to be both a delay and reduction in output level. These two effects are coming from the Capacitor and Resistor respectively.

Delay

In order to simulate the delay, we first have to ground inputs b0 through b8. Then we connect b9 to a pulse voltage source. Once this is done, a 10pF load will be added. This will allow us to simulate the delaly through the DAC (Schematic can be seen below). Since we know that the output resistance of the DAC is R, we can use this value to predict the delay using 0.7RC. In our DAC R=10k ohms and this value must simply be substituted into the equation.

Delay = 0.7RC = 0.7 * 10k ohms * 10pF

Delay = 70ns

This delay can be seen in our simulation below.

Determining the output resistance of the DAC

Discuss what happens if the resistance of the switches isn't small compared to R

If the resistance of the switches isn't small compared to R, the output voltage will be much smaller than input voltage. This is because of the increase in internal resistance.

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